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authorMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>2021-03-04 22:11:01 +0000
committerMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>2021-03-07 10:39:05 +0000
commit238ec4d7d4dba29c8d6d8766351d1dedf84008e0 (patch)
tree944ef2c8552bd2fc67bc29a41aa17eddcd2584c7 /hw
parent023666da792ac465e43dee3bacb21bb781de5cdb (diff)
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esp: add trivial implementation of the ESP_RFLAGS register
The bottom 5 bits contain the number of bytes remaining in the FIFO which is trivial to implement with Fifo8 (the remaining bits are unimplemented and left as 0 for now). Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-41-mark.cave-ayland@ilande.co.uk>
Diffstat (limited to 'hw')
-rw-r--r--hw/scsi/esp.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 34dc58d..8a9b150 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -818,6 +818,10 @@ uint64_t esp_reg_read(ESPState *s, uint32_t saddr)
val = s->rregs[saddr];
}
break;
+ case ESP_RFLAGS:
+ /* Bottom 5 bits indicate number of bytes in FIFO */
+ val = fifo8_num_used(&s->fifo);
+ break;
default:
val = s->rregs[saddr];
break;