diff options
author | Blue Swirl <blauwirbel@gmail.com> | 2010-03-29 19:23:52 +0000 |
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committer | Blue Swirl <blauwirbel@gmail.com> | 2010-03-29 19:23:52 +0000 |
commit | 53b67b3052f39b049bc7c79ae1ce132c90098c6c (patch) | |
tree | 5977097e25ae67ac7ff64392835bf9bba3a73c59 /hw | |
parent | ad96090a01d848df67d70c5259ed8aa321fa8716 (diff) | |
download | qemu-53b67b3052f39b049bc7c79ae1ce132c90098c6c.zip qemu-53b67b3052f39b049bc7c79ae1ce132c90098c6c.tar.gz qemu-53b67b3052f39b049bc7c79ae1ce132c90098c6c.tar.bz2 |
Compile acpi only once
Use qemu_irqs to trigger CMOS S3 and SMI events.
Avoid using kvm.h, which uses CPUState.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'hw')
-rw-r--r-- | hw/acpi.c | 25 | ||||
-rw-r--r-- | hw/mips_malta.c | 3 | ||||
-rw-r--r-- | hw/pc.c | 36 | ||||
-rw-r--r-- | hw/pc.h | 5 |
4 files changed, 47 insertions, 22 deletions
@@ -22,7 +22,6 @@ #include "sysemu.h" #include "i2c.h" #include "smbus.h" -#include "kvm.h" //#define DEBUG @@ -50,6 +49,9 @@ typedef struct PIIX4PMState { uint8_t smb_data[32]; uint8_t smb_index; qemu_irq irq; + qemu_irq cmos_s3; + qemu_irq smi_irq; + int kvm_enabled; } PIIX4PMState; #define RSM_STS (1 << 15) @@ -158,9 +160,9 @@ static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val) was caused by power button */ s->pmsts |= (RSM_STS | PWRBTN_STS); qemu_system_reset_request(); -#if defined(TARGET_I386) - cmos_set_s3_resume(); -#endif + if (s->cmos_s3) { + qemu_irq_raise(s->cmos_s3); + } default: break; } @@ -248,7 +250,9 @@ static void pm_smi_writeb(void *opaque, uint32_t addr, uint32_t val) } if (s->dev.config[0x5b] & (1 << 1)) { - cpu_interrupt(first_cpu, CPU_INTERRUPT_SMI); + if (s->smi_irq) { + qemu_irq_raise(s->smi_irq); + } } } else { s->apms = val; @@ -478,7 +482,7 @@ static void piix4_reset(void *opaque) pci_conf[0x5a] = 0; pci_conf[0x5b] = 0; - if (kvm_enabled()) { + if (s->kvm_enabled) { /* Mark SMM as already inited (until KVM supports SMM). */ pci_conf[0x5B] = 0x02; } @@ -486,7 +490,6 @@ static void piix4_reset(void *opaque) static void piix4_powerdown(void *opaque, int irq, int power_failing) { -#if defined(TARGET_I386) PIIX4PMState *s = opaque; if (!s) { @@ -495,11 +498,11 @@ static void piix4_powerdown(void *opaque, int irq, int power_failing) s->pmsts |= PWRBTN_EN; pm_update_sci(s); } -#endif } i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, - qemu_irq sci_irq) + qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq, + int kvm_enabled) { PIIX4PMState *s; uint8_t *pci_conf; @@ -526,7 +529,7 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); - if (kvm_enabled()) { + if (kvm_enabled) { /* Mark SMM as already inited to prevent SMM from running. KVM does not * support SMM mode. */ pci_conf[0x5B] = 0x02; @@ -553,6 +556,8 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, s->smbus = i2c_init_bus(NULL, "i2c"); s->irq = sci_irq; + s->cmos_s3 = cmos_s3; + s->smi_irq = smi_irq; qemu_register_reset(piix4_reset, s); return s->smbus; diff --git a/hw/mips_malta.c b/hw/mips_malta.c index 9a35d0c..e4e7507 100644 --- a/hw/mips_malta.c +++ b/hw/mips_malta.c @@ -924,7 +924,8 @@ void mips_malta_init (ram_addr_t ram_size, isa_bus_irqs(i8259); pci_piix4_ide_init(pci_bus, hd, piix4_devfn + 1); usb_uhci_piix4_init(pci_bus, piix4_devfn + 2); - smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, isa_reserve_irq(9)); + smbus = piix4_pm_init(pci_bus, piix4_devfn + 3, 0x1100, isa_reserve_irq(9), + NULL, NULL, 0); eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */ for (i = 0; i < 8; i++) { /* TODO: Populate SPD eeprom data. */ @@ -46,6 +46,7 @@ #include "loader.h" #include "elf.h" #include "multiboot.h" +#include "kvm.h" /* output Bochs bios info messages */ //#define DEBUG_BIOS @@ -752,6 +753,26 @@ int cpu_is_bsp(CPUState *env) return env->cpu_index == 0; } +/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) + BIOS will read it and start S3 resume at POST Entry */ +static void cmos_set_s3_resume(void *opaque, int irq, int level) +{ + RTCState *s = opaque; + + if (level) { + rtc_set_memory(s, 0xF, 0xFE); + } +} + +static void acpi_smi_interrupt(void *opaque, int irq, int level) +{ + CPUState *s = opaque; + + if (level) { + cpu_interrupt(s, CPU_INTERRUPT_SMI); + } +} + static CPUState *pc_new_cpu(const char *cpu_model) { CPUState *env; @@ -792,6 +813,8 @@ static void pc_init1(ram_addr_t ram_size, qemu_irq *cpu_irq; qemu_irq *isa_irq; qemu_irq *i8259; + qemu_irq *cmos_s3; + qemu_irq *smi_irq; IsaIrqState *isa_irq_state; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; DriveInfo *fd[MAX_FD]; @@ -1006,9 +1029,12 @@ static void pc_init1(ram_addr_t ram_size, uint8_t *eeprom_buf = qemu_mallocz(8 * 256); /* XXX: make this persistent */ i2c_bus *smbus; + cmos_s3 = qemu_allocate_irqs(cmos_set_s3_resume, rtc_state, 1); + smi_irq = qemu_allocate_irqs(acpi_smi_interrupt, first_cpu, 1); /* TODO: Populate SPD eeprom data. */ smbus = piix4_pm_init(pci_bus, piix3_devfn + 3, 0xb100, - isa_reserve_irq(9)); + isa_reserve_irq(9), *cmos_s3, *smi_irq, + kvm_enabled()); for (i = 0; i < 8; i++) { DeviceState *eeprom; eeprom = qdev_create((BusState *)smbus, "smbus-eeprom"); @@ -1060,14 +1086,6 @@ static void pc_init_isa(ram_addr_t ram_size, initrd_filename, cpu_model, 0); } -/* set CMOS shutdown status register (index 0xF) as S3_resume(0xFE) - BIOS will read it and start S3 resume at POST Entry */ -void cmos_set_s3_resume(void) -{ - if (rtc_state) - rtc_set_memory(rtc_state, 0xF, 0xFE); -} - static QEMUMachine pc_machine = { .name = "pc-0.13", .alias = "pc", @@ -73,7 +73,6 @@ typedef struct RTCState RTCState; RTCState *rtc_init(int base_year); void rtc_set_memory(RTCState *s, int addr, int val); void rtc_set_date(RTCState *s, const struct tm *tm); -void cmos_set_s3_resume(void); /* pc.c */ extern int fd_bootchk; @@ -90,8 +89,10 @@ void acpi_bios_init(void); int acpi_table_add(const char *table_desc); /* acpi_piix.c */ + i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base, - qemu_irq sci_irq); + qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq, + int kvm_enabled); void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr); void piix4_acpi_system_hot_add_init(PCIBus *bus); |