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author | Peter Maydell <peter.maydell@linaro.org> | 2018-08-06 13:34:44 +0100 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2018-08-06 16:19:33 +0100 |
commit | 326049cc8e6079d1ea49dc4b415b8112f0c995bd (patch) | |
tree | 8306c9fd2971773f46f34d525d73fd2d1c61c5ef /hw | |
parent | 7b69454a12510dc84b71c292214c364e499609e7 (diff) | |
download | qemu-326049cc8e6079d1ea49dc4b415b8112f0c995bd.zip qemu-326049cc8e6079d1ea49dc4b415b8112f0c995bd.tar.gz qemu-326049cc8e6079d1ea49dc4b415b8112f0c995bd.tar.bz2 |
hw/intc/arm_gicv3_common: Move post_load hooks to top-level VMSD
Contrary to the the impression given in docs/devel/migration.rst,
the migration code does not run the pre_load hook for a
subsection unless the subsection appears on the wire, and so
this is not a place where you can set the default value for
state for the "subsection not present" case. Instead this needs
to be done in a pre_load hook for whatever is the parent VMSD
of the subsection.
We got this wrong in two of the subsection definitions in
the GICv3 migration structs; fix this.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Message-id: 20180806123445.1459-5-peter.maydell@linaro.org
Diffstat (limited to 'hw')
-rw-r--r-- | hw/intc/arm_gicv3_common.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index e1a8999..8175889 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -73,7 +73,7 @@ static const VMStateDescription vmstate_gicv3_cpu_virt = { } }; -static int icc_sre_el1_reg_pre_load(void *opaque) +static int vmstate_gicv3_cpu_pre_load(void *opaque) { GICv3CPUState *cs = opaque; @@ -97,7 +97,6 @@ const VMStateDescription vmstate_gicv3_cpu_sre_el1 = { .name = "arm_gicv3_cpu/sre_el1", .version_id = 1, .minimum_version_id = 1, - .pre_load = icc_sre_el1_reg_pre_load, .needed = icc_sre_el1_reg_needed, .fields = (VMStateField[]) { VMSTATE_UINT64(icc_sre_el1, GICv3CPUState), @@ -109,6 +108,7 @@ static const VMStateDescription vmstate_gicv3_cpu = { .name = "arm_gicv3_cpu", .version_id = 1, .minimum_version_id = 1, + .pre_load = vmstate_gicv3_cpu_pre_load, .fields = (VMStateField[]) { VMSTATE_UINT32(level, GICv3CPUState), VMSTATE_UINT32(gicr_ctlr, GICv3CPUState), @@ -139,7 +139,7 @@ static const VMStateDescription vmstate_gicv3_cpu = { } }; -static int gicv3_gicd_no_migration_shift_bug_pre_load(void *opaque) +static int gicv3_pre_load(void *opaque) { GICv3State *cs = opaque; @@ -210,7 +210,6 @@ const VMStateDescription vmstate_gicv3_gicd_no_migration_shift_bug = { .version_id = 1, .minimum_version_id = 1, .needed = needed_always, - .pre_load = gicv3_gicd_no_migration_shift_bug_pre_load, .post_load = gicv3_gicd_no_migration_shift_bug_post_load, .fields = (VMStateField[]) { VMSTATE_BOOL(gicd_no_migration_shift_bug, GICv3State), @@ -222,6 +221,7 @@ static const VMStateDescription vmstate_gicv3 = { .name = "arm_gicv3", .version_id = 1, .minimum_version_id = 1, + .pre_load = gicv3_pre_load, .pre_save = gicv3_pre_save, .post_load = gicv3_post_load, .priority = MIG_PRI_GICV3, |