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| author | Peter Maydell <peter.maydell@linaro.org> | 2018-07-23 19:03:37 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-07-24 11:42:15 +0100 |
| commit | 042374c92e83da5c8f906b9b97814a21eac2a09f (patch) | |
| tree | e7dcbcbd5fc61a738fdc6e70cb140570fe4c17f1 /hw | |
| parent | 0c6c43955421764998eb0dd1863ee8b38a3ff1c1 (diff) | |
| download | qemu-042374c92e83da5c8f906b9b97814a21eac2a09f.zip qemu-042374c92e83da5c8f906b9b97814a21eac2a09f.tar.gz qemu-042374c92e83da5c8f906b9b97814a21eac2a09f.tar.bz2 | |
hw/intc/arm_gicv3: Check correct HCR_EL2 bit when routing IRQ
In icc_dir_write() we were incorrectly checking HCR_EL2.FMO
when determining whether IRQ should be routed to EL2; this should
be HCR_EL2.IMO (compare the GICv3 pseudocode ICC_DIR_EL1[]).
Use the correct mask.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180723180337.17378-1-peter.maydell@linaro.org
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/intc/arm_gicv3_cpuif.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 5c89be1..2a60568 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -1550,7 +1550,7 @@ static void icc_dir_write(CPUARMState *env, const ARMCPRegInfo *ri, * tested in cases where we know !IsSecure is true. */ route_fiq_to_el2 = env->cp15.hcr_el2 & HCR_FMO; - route_irq_to_el2 = env->cp15.hcr_el2 & HCR_FMO; + route_irq_to_el2 = env->cp15.hcr_el2 & HCR_IMO; switch (arm_current_el(env)) { case 3: |