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| author | Bin Meng <bmeng.cn@gmail.com> | 2019-09-06 09:20:04 -0700 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@sifive.com> | 2019-09-17 08:42:47 -0700 |
| commit | e8c56787cd78f5d26285120f85bf898f5d3693b9 (patch) | |
| tree | b0fecb271860e7ad6c35fcf5763035e59913e931 /hw | |
| parent | 91c985851dd57df3b003e7bd91f1cf544b3a288d (diff) | |
| download | qemu-e8c56787cd78f5d26285120f85bf898f5d3693b9.zip qemu-e8c56787cd78f5d26285120f85bf898f5d3693b9.tar.gz qemu-e8c56787cd78f5d26285120f85bf898f5d3693b9.tar.bz2 | |
riscv: hart: Add a "hartid-base" property to RISC-V hart array
At present each hart's hartid in a RISC-V hart array is assigned
the same value of its index in the hart array. But for a system
that has multiple hart arrays, this is not the case any more.
Add a new "hartid-base" property so that hartid number can be
assigned based on the property value.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
Diffstat (limited to 'hw')
| -rw-r--r-- | hw/riscv/riscv_hart.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 6620e41..5b98227 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -29,6 +29,7 @@ static Property riscv_harts_props[] = { DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1), + DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0), DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), DEFINE_PROP_END_OF_LIST(), }; @@ -47,7 +48,7 @@ static void riscv_hart_realize(RISCVHartArrayState *s, int idx, object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], sizeof(RISCVCPU), cpu_type, &error_abort, NULL); - s->harts[idx].env.mhartid = idx; + s->harts[idx].env.mhartid = s->hartid_base + idx; qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); object_property_set_bool(OBJECT(&s->harts[idx]), true, "realized", &err); |