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authorPeter Crosthwaite <peter.crosthwaite@xilinx.com>2013-06-03 17:17:41 +0100
committerPeter Maydell <peter.maydell@linaro.org>2013-06-03 17:17:41 +0100
commit87920b44a1e04a45bf74ee0a88a2dfa51c65acdb (patch)
tree8abd0ef8458dda854108872264c3ac7382ee61c7 /hw
parent6b91f0155b9338b7fa53d1d64f4e40c43a5d3bba (diff)
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xilinx_spips: Make interrupts clear on read
By default these interrupts are clear on read. Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@gmail.com> Message-id: 999ff0091ed3cc3969a431bf55c00ef934cecc8e.1369117359.git.peter.crosthwaite@xilinx.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw')
-rw-r--r--hw/ssi/xilinx_spips.c4
1 files changed, 4 insertions, 0 deletions
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index 734adf0..261d948 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -330,6 +330,10 @@ static uint64_t xilinx_spips_read(void *opaque, hwaddr addr,
mask = 0x0002FFFF;
break;
case R_INTR_STATUS:
+ ret = s->regs[addr] & IXR_ALL;
+ s->regs[addr] = 0;
+ DB_PRINT("addr=" TARGET_FMT_plx " = %x\n", addr * 4, ret);
+ return ret;
case R_INTR_MASK:
mask = IXR_ALL;
break;