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author | Anthony Liguori <aliguori@us.ibm.com> | 2011-12-04 12:22:06 -0600 |
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committer | Anthony Liguori <aliguori@us.ibm.com> | 2012-01-27 10:50:50 -0600 |
commit | 40021f08882aaef93c66c8c740087b6d3031b63a (patch) | |
tree | a0429c040df66503d807770a3b89da9a0c70d8ac /hw/xio3130_downstream.c | |
parent | 6e4ec3f9bb32d6f41e4fb30b872d2b7b084bc9a9 (diff) | |
download | qemu-40021f08882aaef93c66c8c740087b6d3031b63a.zip qemu-40021f08882aaef93c66c8c740087b6d3031b63a.tar.gz qemu-40021f08882aaef93c66c8c740087b6d3031b63a.tar.bz2 |
pci: convert to QEMU Object Model
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'hw/xio3130_downstream.c')
-rw-r--r-- | hw/xio3130_downstream.c | 59 |
1 files changed, 33 insertions, 26 deletions
diff --git a/hw/xio3130_downstream.c b/hw/xio3130_downstream.c index d3c387d..6d625cb 100644 --- a/hw/xio3130_downstream.c +++ b/hw/xio3130_downstream.c @@ -47,7 +47,7 @@ static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address, static void xio3130_downstream_reset(DeviceState *qdev) { - PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev); + PCIDevice *d = PCI_DEVICE(qdev); msi_reset(d); pcie_cap_deverr_reset(d); pcie_cap_slot_reset(d); @@ -167,31 +167,38 @@ static const VMStateDescription vmstate_xio3130_downstream = { } }; -static PCIDeviceInfo xio3130_downstream_info = { - .qdev.name = "xio3130-downstream", - .qdev.desc = "TI X3130 Downstream Port of PCI Express Switch", - .qdev.size = sizeof(PCIESlot), - .qdev.reset = xio3130_downstream_reset, - .qdev.vmsd = &vmstate_xio3130_downstream, - - .is_express = 1, - .is_bridge = 1, - .config_write = xio3130_downstream_write_config, - .init = xio3130_downstream_initfn, - .exit = xio3130_downstream_exitfn, - .vendor_id = PCI_VENDOR_ID_TI, - .device_id = PCI_DEVICE_ID_TI_XIO3130D, - .revision = XIO3130_REVISION, - - .qdev.props = (Property[]) { - DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0), - DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), - DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), - DEFINE_PROP_UINT16("aer_log_max", PCIESlot, - port.br.dev.exp.aer_log.log_max, - PCIE_AER_LOG_MAX_DEFAULT), - DEFINE_PROP_END_OF_LIST(), - } +static Property xio3130_downstream_properties[] = { + DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0), + DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), + DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), + DEFINE_PROP_UINT16("aer_log_max", PCIESlot, + port.br.dev.exp.aer_log.log_max, + PCIE_AER_LOG_MAX_DEFAULT), + DEFINE_PROP_END_OF_LIST(), +}; + +static void xio3130_downstream_class_init(ObjectClass *klass, void *data) +{ + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + k->is_express = 1; + k->is_bridge = 1; + k->config_write = xio3130_downstream_write_config; + k->init = xio3130_downstream_initfn; + k->exit = xio3130_downstream_exitfn; + k->vendor_id = PCI_VENDOR_ID_TI; + k->device_id = PCI_DEVICE_ID_TI_XIO3130D; + k->revision = XIO3130_REVISION; +} + +static DeviceInfo xio3130_downstream_info = { + .name = "xio3130-downstream", + .desc = "TI X3130 Downstream Port of PCI Express Switch", + .size = sizeof(PCIESlot), + .reset = xio3130_downstream_reset, + .vmsd = &vmstate_xio3130_downstream, + .props = xio3130_downstream_properties, + .class_init = xio3130_downstream_class_init, }; static void xio3130_downstream_register(void) |