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authorAndrew Jeffery <andrew@aj.id.au>2021-09-20 08:50:59 +0200
committerCédric Le Goater <clg@kaod.org>2021-09-20 08:50:59 +0200
commit74b67e1f9de37f88e9a6062075ef647ae61d68df (patch)
treebcf20b72cd56e794f9208aaf9545a43e478005e6 /hw/watchdog
parent709098fd37307a810ae4b8958ade348745b5c0fe (diff)
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watchdog: aspeed: Fix sequential control writes
The logic in the handling for the control register required toggling the enable state for writes to stick. Rework the condition chain to allow sequential writes that do not update the enable state. Fixes: 854123bf8d4b ("wdt: Add Aspeed watchdog device model") Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210709053107.1829304-3-andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Diffstat (limited to 'hw/watchdog')
-rw-r--r--hw/watchdog/wdt_aspeed.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c
index faa3d35..69c37af 100644
--- a/hw/watchdog/wdt_aspeed.c
+++ b/hw/watchdog/wdt_aspeed.c
@@ -166,6 +166,8 @@ static void aspeed_wdt_write(void *opaque, hwaddr offset, uint64_t data,
} else if (!enable && aspeed_wdt_is_enabled(s)) {
s->regs[WDT_CTRL] = data;
timer_del(s->timer);
+ } else {
+ s->regs[WDT_CTRL] = data;
}
break;
case WDT_RESET_WIDTH: