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authorPeter Maydell <peter.maydell@linaro.org>2018-07-03 16:04:41 +0100
committerPeter Maydell <peter.maydell@linaro.org>2018-07-03 16:04:41 +0100
commitf988c7e191141e92de2059d04a5f9a9bb01f399c (patch)
treeaec6939093a0641f00449530b3e09c0604073078 /hw/usb
parentb07cd3e748b3f27a17c27afeee578dc4eedb8dd5 (diff)
parentdfc84745bbaa0fea2abc8575dd349f6e4bb7edc7 (diff)
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Merge remote-tracking branch 'remotes/shorne/tags/pull-or-20180703' into staging
OpenRISC cleanups and Fixes for QEMU 3.0 Mostly patches from Richard Henderson fixing multiple things: * Fix singlestepping in GDB. * Use more TB linking. * Fixes to exit TB after updating SPRs to enable registering of state changes. * Significant optimizations and refactors to the TLB * Split out disassembly from translation. * Add qemu-or1k to qemu-binfmt-conf.sh. * Implement signal handling for linux-user. Then there are a few fixups from me: * Fix delay slot detections to match hardware, this was masking a bug in the linus kernel. * Fix stores to the PIC mask register # gpg: Signature made Tue 03 Jul 2018 14:44:10 BST # gpg: using RSA key C3B31C2D5E6627E4 # gpg: Good signature from "Stafford Horne <shorne@gmail.com>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: D9C4 7354 AEF8 6C10 3A25 EFF1 C3B3 1C2D 5E66 27E4 * remotes/shorne/tags/pull-or-20180703: (25 commits) target/openrisc: Fix writes to interrupt mask register target/openrisc: Fix delay slot exception flag to match spec linux-user: Fix struct sigaltstack for openrisc linux-user: Implement signals for openrisc target/openrisc: Add support in scripts/qemu-binfmt-conf.sh target/openrisc: Reorg tlb lookup target/openrisc: Increase the TLB size target/openrisc: Stub out handle_mmu_fault for softmmu target/openrisc: Use identical sizes for ITLB and DTLB target/openrisc: Fix cpu_mmu_index target/openrisc: Fix tlb flushing in mtspr target/openrisc: Reduce tlb to a single dimension target/openrisc: Merge mmu_helper.c into mmu.c target/openrisc: Remove indirect function calls for mmu target/openrisc: Merge tlb allocation into CPUOpenRISCState target/openrisc: Form the spr index from tcg target/openrisc: Exit the TB after l.mtspr target/openrisc: Split out is_user target/openrisc: Link more translation blocks target/openrisc: Fix singlestep_enabled ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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