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authorRuimei Yan <ruimei.yan@windriver.com>2021-05-21 10:42:24 +0800
committerGerd Hoffmann <kraxel@redhat.com>2021-05-28 09:10:20 +0200
commitfc967aad408eb4777b099d17ada1f39be5f6fd2e (patch)
tree45b56123354608ea6b9fa00361eb8686e4e37656 /hw/usb/hcd-xhci.c
parent3c6151cd11ae7e4a7dae10f8c17ab1fe2f0a73bf (diff)
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hw/usb: hcd-xhci-pci: Fix spec violation of IP flag for MSI/MSI-X
Per xHCI spec v1.2 chapter 4.17.5 page 296: If MSI or MSI-X interrupts are enabled, Interrupt Pending (IP) shall be cleared automatically when the PCI dword write generated by the interrupt assertion is complete. Currently QEMU does not clear the IP flag in the MSI / MSI-X mode. This causes subsequent spurious interrupt to be delivered to guests. To solve this, we change the xhci intr_raise() hook routine to have a bool return value that is passed to its caller (the xhci core), with true indicating that IP should be self-cleared. Fixes: 62c6ae04cf43 ("xhci: Initial xHCI implementation") Fixes: 4c47f800631a ("xhci: add msix support") Signed-off-by: Ruimei Yan <ruimei.yan@windriver.com> [bmeng: move IP clear codes from xhci pci to xhci core] Signed-off-by: Bin Meng <bin.meng@windriver.com> Message-Id: <20210521024224.2277634-2-bmeng.cn@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Diffstat (limited to 'hw/usb/hcd-xhci.c')
-rw-r--r--hw/usb/hcd-xhci.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c
index 46212b1..e017000 100644
--- a/hw/usb/hcd-xhci.c
+++ b/hw/usb/hcd-xhci.c
@@ -551,7 +551,9 @@ static void xhci_intr_update(XHCIState *xhci, int v)
level = 1;
}
if (xhci->intr_raise) {
- xhci->intr_raise(xhci, 0, level);
+ if (xhci->intr_raise(xhci, 0, level)) {
+ xhci->intr[0].iman &= ~IMAN_IP;
+ }
}
}
if (xhci->intr_update) {
@@ -579,7 +581,9 @@ static void xhci_intr_raise(XHCIState *xhci, int v)
return;
}
if (xhci->intr_raise) {
- xhci->intr_raise(xhci, v, true);
+ if (xhci->intr_raise(xhci, v, true)) {
+ xhci->intr[v].iman &= ~IMAN_IP;
+ }
}
}