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author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-25 18:50:28 +0000 |
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committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-05-25 18:50:28 +0000 |
commit | 20c9f095c4536e64e60432a5c72fce38e8306cbb (patch) | |
tree | fe68375301d78efc0eb73138da36199a00bcde7a /hw/sun4u.c | |
parent | 8d05ea8a33c9d450d2a3079e967c69ea38ec28ba (diff) | |
download | qemu-20c9f095c4536e64e60432a5c72fce38e8306cbb.zip qemu-20c9f095c4536e64e60432a5c72fce38e8306cbb.tar.gz qemu-20c9f095c4536e64e60432a5c72fce38e8306cbb.tar.bz2 |
Implement Sparc64 CPU timers using ptimers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2860 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/sun4u.c')
-rw-r--r-- | hw/sun4u.c | 41 |
1 files changed, 41 insertions, 0 deletions
@@ -282,7 +282,35 @@ void qemu_system_powerdown(void) static void main_cpu_reset(void *opaque) { CPUState *env = opaque; + cpu_reset(env); + ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1); + ptimer_run(env->tick, 0); + ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1); + ptimer_run(env->stick, 0); + ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1); + ptimer_run(env->hstick, 0); +} + +void tick_irq(void *opaque) +{ + CPUState *env = opaque; + + cpu_interrupt(env, CPU_INTERRUPT_TIMER); +} + +void stick_irq(void *opaque) +{ + CPUState *env = opaque; + + cpu_interrupt(env, CPU_INTERRUPT_TIMER); +} + +void hstick_irq(void *opaque) +{ + CPUState *env = opaque; + + cpu_interrupt(env, CPU_INTERRUPT_TIMER); } static const int ide_iobase[2] = { 0x1f0, 0x170 }; @@ -311,6 +339,7 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device, long prom_offset, initrd_size, kernel_size; PCIBus *pci_bus; const sparc_def_t *def; + QEMUBH *bh; linux_boot = (kernel_filename != NULL); @@ -324,8 +353,20 @@ static void sun4u_init(int ram_size, int vga_ram_size, int boot_device, } env = cpu_init(); cpu_sparc_register(env, def); + bh = qemu_bh_new(tick_irq, env); + env->tick = ptimer_init(bh); + ptimer_set_period(env->tick, 1ULL); + + bh = qemu_bh_new(stick_irq, env); + env->stick = ptimer_init(bh); + ptimer_set_period(env->stick, 1ULL); + + bh = qemu_bh_new(hstick_irq, env); + env->hstick = ptimer_init(bh); + ptimer_set_period(env->hstick, 1ULL); register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); qemu_register_reset(main_cpu_reset, env); + main_cpu_reset(env); /* allocate RAM */ cpu_register_physical_memory(0, ram_size, 0); |