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authorChris Rauer <crauer@google.com>2023-04-03 16:12:30 +0100
committerPeter Maydell <peter.maydell@linaro.org>2023-04-03 16:12:30 +0100
commita0eaa126af3c5a43937a22c58cfb9bb36e4a5001 (patch)
treebdbef633077156b97c991c79efd5bbd27ba67168 /hw/ssi
parent782781e85decfd85a6d9b064be741fb30d4fd307 (diff)
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hw/ssi: Fix Linux driver init issue with xilinx_spi
The problem is that the Linux driver expects the master transaction inhibit bit(R_SPICR_MTI) to be set during driver initialization so that it can detect the fifo size but QEMU defaults it to zero out of reset. The datasheet indicates this bit is active on reset. See page 25, SPI Control Register section: https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf Signed-off-by: Chris Rauer <crauer@google.com> Message-id: 20230323182811.2641044-1-crauer@google.com Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/ssi')
-rw-r--r--hw/ssi/xilinx_spi.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c
index 5529276..d4de2e7 100644
--- a/hw/ssi/xilinx_spi.c
+++ b/hw/ssi/xilinx_spi.c
@@ -156,6 +156,7 @@ static void xlx_spi_do_reset(XilinxSPI *s)
txfifo_reset(s);
s->regs[R_SPISSR] = ~0;
+ s->regs[R_SPICR] = R_SPICR_MTI;
xlx_spi_update_irq(s);
xlx_spi_update_cs(s);
}