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author | Paul Brook <paul@codesourcery.com> | 2009-05-14 22:35:09 +0100 |
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committer | Paul Brook <paul@codesourcery.com> | 2009-05-14 22:35:09 +0100 |
commit | 90d37239d4051281d2882117efc73020046c32ca (patch) | |
tree | e9861ffff211a45026d66271e4889b7d410e1a49 /hw/ssi.h | |
parent | 1de9610c8ff80aa2a47b6cbe8c198b935916feda (diff) | |
download | qemu-90d37239d4051281d2882117efc73020046c32ca.zip qemu-90d37239d4051281d2882117efc73020046c32ca.tar.gz qemu-90d37239d4051281d2882117efc73020046c32ca.tar.bz2 |
SSP bus framework
Signed-off-by: Paul Brook <paul@codesourcery.com>
Diffstat (limited to 'hw/ssi.h')
-rw-r--r-- | hw/ssi.h | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/hw/ssi.h b/hw/ssi.h new file mode 100644 index 0000000..d9865e6 --- /dev/null +++ b/hw/ssi.h @@ -0,0 +1,41 @@ +/* QEMU Synchronous Serial Interface support. */ + +/* In principle SSI is a point-point interface. As such the qemu + implementation has a single slave device on a "bus". + However it is fairly common for boards to have multiple slaves + connected to a single master, and select devices with an external + chip select. This is implemented in qemu by having an explicit mux device. + It is assumed that master and slave are both using the same transfer width. + */ + +#ifndef QEMU_SSI_H +#define QEMU_SSI_H + +#include "qdev.h" + +typedef struct SSISlave SSISlave; + +/* Slave devices. */ +typedef struct { + void (*init)(SSISlave *dev); + uint32_t (*transfer)(SSISlave *dev, uint32_t val); +} SSISlaveInfo; + +struct SSISlave { + DeviceState qdev; + SSISlaveInfo *info; +}; + +#define SSI_SLAVE_FROM_QDEV(dev) DO_UPCAST(SSISlave, qdev, dev) +#define FROM_SSI_SLAVE(type, dev) DO_UPCAST(type, ssidev, dev) + +void ssi_register_slave(const char *name, int size, SSISlaveInfo *info); + +DeviceState *ssi_create_slave(SSIBus *bus, const char *name); + +/* Master interface. */ +SSIBus *ssi_create_bus(void); + +uint32_t ssi_transfer(SSIBus *bus, uint32_t val); + +#endif |