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authorPaolo Bonzini <pbonzini@redhat.com>2013-07-22 15:54:29 +0200
committerAnthony Liguori <aliguori@us.ibm.com>2013-07-25 08:12:27 -0500
commitb23ea25f5098f576d10a8833bc60b8f8394f9b0b (patch)
treeeb4d3ae428194d34cc8a1c2fdc8a3cb7b8b7ff21 /hw/sh4
parentb332d24a8e1290954029814d09156b06ede358e2 (diff)
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sh4: unbreak r2d
... by making sh_pci a subclass of TYPE_PCI_HOST_BRIDGE. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> Reviewed-by: Anthony Liguori <aliguori@us.ibm.com> Message-id: 1374501278-31549-20-git-send-email-pbonzini@redhat.com Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
Diffstat (limited to 'hw/sh4')
-rw-r--r--hw/sh4/sh_pci.c39
1 files changed, 25 insertions, 14 deletions
diff --git a/hw/sh4/sh_pci.c b/hw/sh4/sh_pci.c
index 53e9eb8..e81176a 100644
--- a/hw/sh4/sh_pci.c
+++ b/hw/sh4/sh_pci.c
@@ -28,9 +28,14 @@
#include "qemu/bswap.h"
#include "exec/address-spaces.h"
+#define TYPE_SH_PCI_HOST_BRIDGE "sh_pci"
+
+#define SH_PCI_HOST_BRIDGE(obj) \
+ OBJECT_CHECK(SHPCIState, (obj), TYPE_SH_PCI_HOST_BRIDGE)
+
typedef struct SHPCIState {
- SysBusDevice busdev;
- PCIBus *bus;
+ PCIHostState parent_obj;
+
PCIDevice *dev;
qemu_irq irq[4];
MemoryRegion memconfig_p4;
@@ -45,6 +50,8 @@ static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val,
unsigned size)
{
SHPCIState *pcic = p;
+ PCIHostState *phb = PCI_HOST_BRIDGE(pcic);
+
switch(addr) {
case 0 ... 0xfc:
cpu_to_le32w((uint32_t*)(pcic->dev->config + addr), val);
@@ -64,7 +71,7 @@ static void sh_pci_reg_write (void *p, hwaddr addr, uint64_t val,
}
break;
case 0x220:
- pci_data_write(pcic->bus, pcic->par, val, 4);
+ pci_data_write(phb->bus, pcic->par, val, 4);
break;
}
}
@@ -73,6 +80,8 @@ static uint64_t sh_pci_reg_read (void *p, hwaddr addr,
unsigned size)
{
SHPCIState *pcic = p;
+ PCIHostState *phb = PCI_HOST_BRIDGE(pcic);
+
switch(addr) {
case 0 ... 0xfc:
return le32_to_cpup((uint32_t*)(pcic->dev->config + addr));
@@ -83,7 +92,7 @@ static uint64_t sh_pci_reg_read (void *p, hwaddr addr,
case 0x1c8:
return pcic->iobr;
case 0x220:
- return pci_data_read(pcic->bus, pcic->par, 4);
+ return pci_data_read(phb->bus, pcic->par, 4);
}
return 0;
}
@@ -112,19 +121,21 @@ static void sh_pci_set_irq(void *opaque, int irq_num, int level)
static int sh_pci_device_init(SysBusDevice *dev)
{
+ PCIHostState *phb;
SHPCIState *s;
int i;
- s = FROM_SYSBUS(SHPCIState, dev);
+ s = SH_PCI_HOST_BRIDGE(dev);
+ phb = PCI_HOST_BRIDGE(s);
for (i = 0; i < 4; i++) {
sysbus_init_irq(dev, &s->irq[i]);
}
- s->bus = pci_register_bus(&s->busdev.qdev, "pci",
- sh_pci_set_irq, sh_pci_map_irq,
- s->irq,
- get_system_memory(),
- get_system_io(),
- PCI_DEVFN(0, 0), 4, TYPE_PCI_BUS);
+ phb->bus = pci_register_bus(DEVICE(dev), "pci",
+ sh_pci_set_irq, sh_pci_map_irq,
+ s->irq,
+ get_system_memory(),
+ get_system_io(),
+ PCI_DEVFN(0, 0), 4, TYPE_PCI_BUS);
memory_region_init_io(&s->memconfig_p4, OBJECT(s), &sh_pci_reg_ops, s,
"sh_pci", 0x224);
memory_region_init_alias(&s->memconfig_a7, OBJECT(s), "sh_pci.2",
@@ -136,7 +147,7 @@ static int sh_pci_device_init(SysBusDevice *dev)
s->iobr = 0xfe240000;
memory_region_add_subregion(get_system_memory(), s->iobr, &s->isa);
- s->dev = pci_create_simple(s->bus, PCI_DEVFN(0, 0), "sh_pci_host");
+ s->dev = pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "sh_pci_host");
return 0;
}
@@ -172,8 +183,8 @@ static void sh_pci_device_class_init(ObjectClass *klass, void *data)
}
static const TypeInfo sh_pci_device_info = {
- .name = "sh_pci",
- .parent = TYPE_SYS_BUS_DEVICE,
+ .name = TYPE_SH_PCI_HOST_BRIDGE,
+ .parent = TYPE_PCI_HOST_BRIDGE,
.instance_size = sizeof(SHPCIState),
.class_init = sh_pci_device_class_init,
};