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author | Aurelien Jarno <aurelien@aurel32.net> | 2015-06-03 23:16:43 +0200 |
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committer | Aurelien Jarno <aurelien@aurel32.net> | 2015-06-12 12:02:48 +0200 |
commit | 563807520ff19e6ed2d40695f543f1fba7ba432f (patch) | |
tree | c43cf3c81b0a95f7686a62d2363cde98846de7b9 /hw/sh4 | |
parent | e42fd944f02dda893fc8773959d6db75f2a49367 (diff) | |
download | qemu-563807520ff19e6ed2d40695f543f1fba7ba432f.zip qemu-563807520ff19e6ed2d40695f543f1fba7ba432f.tar.gz qemu-563807520ff19e6ed2d40695f543f1fba7ba432f.tar.bz2 |
sh4/r2d: convert to new MMIO accessor style
The documentation is clear to use 16-bit accesses for all registers.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Diffstat (limited to 'hw/sh4')
-rw-r--r-- | hw/sh4/r2d.c | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index 4221060..5e22ed7 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -127,7 +127,7 @@ static void r2d_fpga_irq_set(void *opaque, int n, int level) update_irl(fpga); } -static uint32_t r2d_fpga_read(void *opaque, hwaddr addr) +static uint64_t r2d_fpga_read(void *opaque, hwaddr addr, unsigned int size) { r2d_fpga_t *s = opaque; @@ -146,7 +146,7 @@ static uint32_t r2d_fpga_read(void *opaque, hwaddr addr) } static void -r2d_fpga_write(void *opaque, hwaddr addr, uint32_t value) +r2d_fpga_write(void *opaque, hwaddr addr, uint64_t value, unsigned int size) { r2d_fpga_t *s = opaque; @@ -170,10 +170,10 @@ r2d_fpga_write(void *opaque, hwaddr addr, uint32_t value) } static const MemoryRegionOps r2d_fpga_ops = { - .old_mmio = { - .read = { r2d_fpga_read, r2d_fpga_read, NULL, }, - .write = { r2d_fpga_write, r2d_fpga_write, NULL, }, - }, + .read = r2d_fpga_read, + .write = r2d_fpga_write, + .impl.min_access_size = 2, + .impl.max_access_size = 2, .endianness = DEVICE_NATIVE_ENDIAN, }; |