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authorBALATON Zoltan <balaton@eik.bme.hu>2021-10-29 23:02:09 +0200
committerPhilippe Mathieu-Daudé <f4bug@amsat.org>2021-10-30 11:46:39 +0200
commit221389657aa77ced7a17936747f288193e321d3f (patch)
treefc025344ea89218c3001f7c1dbd4528a535df7e1 /hw/sh4/sh7750.c
parentb3793b8a9183d6019f557263bbddd647e1918394 (diff)
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hw/sh4: Coding style: Fix multi-line comments
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Yoshinori Sato <ysato@users.sourceforge.jp> Message-Id: <3f192c699f4e5949ec0fcc436e5610f50afe2dbf.1635541329.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'hw/sh4/sh7750.c')
-rw-r--r--hw/sh4/sh7750.c22
1 files changed, 12 insertions, 10 deletions
diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c
index 2a175bf..2539924 100644
--- a/hw/sh4/sh7750.c
+++ b/hw/sh4/sh7750.c
@@ -82,9 +82,10 @@ static inline int has_bcr3_and_bcr4(SH7750State * s)
{
return s->cpu->env.features & SH_FEATURE_BCR3_AND_BCR4;
}
-/**********************************************************************
- I/O ports
-**********************************************************************/
+
+/*
+ * I/O ports
+ */
int sh7750_register_io_device(SH7750State * s, sh7750_io_device * device)
{
@@ -194,9 +195,9 @@ static void portb_changed(SH7750State * s, uint16_t prev)
gen_port_interrupts(s);
}
-/**********************************************************************
- Memory
-**********************************************************************/
+/*
+ * Memory
+ */
static void error_access(const char *kind, hwaddr addr)
{
@@ -491,7 +492,8 @@ static const MemoryRegionOps sh7750_mem_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-/* sh775x interrupt controller tables for sh_intc.c
+/*
+ * sh775x interrupt controller tables for sh_intc.c
* stolen from linux/arch/sh/kernel/cpu/sh4/setup-sh7750.c
*/
@@ -642,9 +644,9 @@ static struct intc_group groups_irl[] = {
IRL_7, IRL_8, IRL_9, IRL_A, IRL_B, IRL_C, IRL_D, IRL_E),
};
-/**********************************************************************
- Memory mapped cache and TLB
-**********************************************************************/
+/*
+ * Memory mapped cache and TLB
+ */
#define MM_REGION_MASK 0x07000000
#define MM_ICACHE_ADDR (0)