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authorMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>2021-03-04 22:10:52 +0000
committerMark Cave-Ayland <mark.cave-ayland@ilande.co.uk>2021-03-07 10:39:05 +0000
commitbb27b13d183a4fdf8d63072861e03d320e41cb0e (patch)
treed3fb37dec96e0c38b32b00b237a466902c7916b5 /hw/scsi/esp.c
parentcf1b8286007a5a12f7d42d484b8ac0e031038e2e (diff)
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esp: implement FIFO flush command
At this point it is now possible to properly implement the FIFO flush command without causing guest errors. Signed-off-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk> Reviewed-by: Laurent Vivier <laurent@vivier.eu> Message-Id: <20210304221103.6369-32-mark.cave-ayland@ilande.co.uk>
Diffstat (limited to 'hw/scsi/esp.c')
-rw-r--r--hw/scsi/esp.c2
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 2dded90..6aae6f9 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -769,6 +769,8 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
case CMD_FLUSH:
trace_esp_mem_writeb_cmd_flush(val);
/*s->ti_size = 0;*/
+ s->ti_wptr = 0;
+ s->ti_rptr = 0;
s->rregs[ESP_RINTR] = INTR_FC;
s->rregs[ESP_RSEQ] = 0;
s->rregs[ESP_RFLAGS] = 0;