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author | Peter Maydell <peter.maydell@linaro.org> | 2020-12-18 11:12:35 +0000 |
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committer | Peter Maydell <peter.maydell@linaro.org> | 2020-12-18 11:12:35 +0000 |
commit | a05f8ecd88f15273d033b6f044b850a8af84a5b8 (patch) | |
tree | f7e62273c6e9697bd2cc28a88e4aad8ef21adc69 /hw/rtc | |
parent | 75ee62ac606bfc9eb59310b9446df3434bf6e8c2 (diff) | |
parent | d31e970a01e7399b9cd43ec0dc00c857d968987e (diff) | |
download | qemu-a05f8ecd88f15273d033b6f044b850a8af84a5b8.zip qemu-a05f8ecd88f15273d033b6f044b850a8af84a5b8.tar.gz qemu-a05f8ecd88f15273d033b6f044b850a8af84a5b8.tar.bz2 |
Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20201217-1' into staging
A collection of RISC-V improvements:
- Improve the sifive_u DTB generation
- Add QSPI NOR flash to Microchip PFSoC
- Fix a bug in the Hypervisor HLVX/HLV/HSV instructions
- Fix some mstatus mask defines
- Ibex PLIC improvements
- OpenTitan memory layout update
- Initial steps towards support for 32-bit CPUs on 64-bit builds
# gpg: Signature made Fri 18 Dec 2020 05:59:42 GMT
# gpg: using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8 CE8F 21E1 0D29 DF97 7054
* remotes/alistair/tags/pull-riscv-to-apply-20201217-1: (23 commits)
riscv/opentitan: Update the OpenTitan memory layout
hw/riscv: Use the CPU to determine if 32-bit
target/riscv: cpu: Set XLEN independently from target
target/riscv: csr: Remove compile time XLEN checks
target/riscv: cpu_helper: Remove compile time XLEN checks
target/riscv: cpu: Remove compile time XLEN checks
target/riscv: Specify the XLEN for CPUs
target/riscv: Add a riscv_cpu_is_32bit() helper function
target/riscv: fpu_helper: Match function defs in HELPER macros
hw/riscv: sifive_u: Remove compile time XLEN checks
hw/riscv: spike: Remove compile time XLEN checks
hw/riscv: virt: Remove compile time XLEN checks
hw/riscv: boot: Remove compile time XLEN checks
riscv: virt: Remove target macro conditionals
riscv: spike: Remove target macro conditionals
target/riscv: Add a TYPE_RISCV_CPU_BASE CPU
hw/riscv: Expand the is 32-bit check to support more CPUs
intc/ibex_plic: Clear interrupts that occur during claim process
target/riscv: Fix definition of MSTATUS_TW and MSTATUS_TSR
target/riscv: Fix the bug of HLVX/HLV/HSV
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat (limited to 'hw/rtc')
0 files changed, 0 insertions, 0 deletions