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| author | Alistair Francis <alistair.francis@wdc.com> | 2021-06-18 17:27:54 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-06-24 05:00:12 -0700 |
| commit | df41cbd6bfa55dc3e69834f4402dbf776062c26e (patch) | |
| tree | 5f8c06787125e59d9c3dabb1a59dc3dd7c6853fa /hw/riscv | |
| parent | bdc36ce649e2985225fcf9ab4958698fcafb04e9 (diff) | |
| download | qemu-df41cbd6bfa55dc3e69834f4402dbf776062c26e.zip qemu-df41cbd6bfa55dc3e69834f4402dbf776062c26e.tar.gz qemu-df41cbd6bfa55dc3e69834f4402dbf776062c26e.tar.bz2 | |
hw/timer: Initial commit of Ibex Timer
Add support for the Ibex timer. This is used with the RISC-V
mtime/mtimecmp similar to the SiFive CLINT.
We currently don't support changing the prescale or the timervalue.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: 716fdea2244515ce86a2c46fe69467d013c03147.1624001156.git.alistair.francis@wdc.com
Diffstat (limited to 'hw/riscv')
0 files changed, 0 insertions, 0 deletions