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| author | Bin Meng <bin.meng@windriver.com> | 2020-09-01 09:38:58 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:18 -0700 |
| commit | 73f6ed97acdbf7aec72d368fd5e16c00e04ac172 (patch) | |
| tree | b8e8f5ca6ba769ca3ac776411be5f2d75d72781b /hw/riscv | |
| parent | 4100d5e6dc28cdd89d3eec6e4ddeb9d1a159c330 (diff) | |
| download | qemu-73f6ed97acdbf7aec72d368fd5e16c00e04ac172.zip qemu-73f6ed97acdbf7aec72d368fd5e16c00e04ac172.tar.gz qemu-73f6ed97acdbf7aec72d368fd5e16c00e04ac172.tar.bz2 | |
target/riscv: cpu: Set reset vector based on the configured property value
Now that we have the newly introduced 'resetvec' property in the
RISC-V CPU and HART, instead of hard-coding the reset vector addr
in the CPU's instance_init(), move that to riscv_cpu_realize()
based on the configured property value from the RISC-V machines.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1598924352-89526-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/opentitan.c | 1 | ||||
| -rw-r--r-- | hw/riscv/sifive_e.c | 1 | ||||
| -rw-r--r-- | hw/riscv/sifive_u.c | 2 |
3 files changed, 4 insertions, 0 deletions
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 23ba3b4..0531bd8 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -111,6 +111,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) &error_abort); object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, &error_abort); + object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8090, &error_abort); sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_abort); /* Boot ROM */ diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index ca55cc4..cd7560d 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -177,6 +177,7 @@ static void sifive_e_soc_init(Object *obj) object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, &error_abort); + object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_abort); object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio, TYPE_SIFIVE_GPIO); } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index a48046c..404d5e6 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -611,6 +611,7 @@ static void sifive_u_soc_instance_init(Object *obj) qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); + qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004); object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER); qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); @@ -620,6 +621,7 @@ static void sifive_u_soc_instance_init(Object *obj) qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU); + qdev_prop_set_uint64(DEVICE(&s->u_cpus), "resetvec", 0x1004); object_initialize_child(obj, "prci", &s->prci, TYPE_SIFIVE_U_PRCI); object_initialize_child(obj, "otp", &s->otp, TYPE_SIFIVE_U_OTP); |