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author | Richard Henderson <richard.henderson@linaro.org> | 2022-10-24 09:33:37 +1000 |
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committer | Alistair Francis <alistair.francis@wdc.com> | 2023-01-06 10:42:55 +1000 |
commit | 2e3a933abb8bd965db99375bfc341d2d46480995 (patch) | |
tree | b77dee3d7f8bc6fb8c97c682ab8efc41a9e0d7ec /hw/riscv | |
parent | 9b246685b3dbbf21800e3a9a09f8bed384a1fb37 (diff) | |
download | qemu-2e3a933abb8bd965db99375bfc341d2d46480995.zip qemu-2e3a933abb8bd965db99375bfc341d2d46480995.tar.gz qemu-2e3a933abb8bd965db99375bfc341d2d46480995.tar.bz2 |
tcg/riscv: Fix base register for user-only qemu_ld/st
When guest_base != 0, we were not coordinating the usage of
TCG_REG_TMP0 as base properly, leading to a previous zero-extend
of the input address being discarded.
Shuffle the alignment check to the front, because that does not
depend on the zero-extend, and it keeps the register usage clear.
Set base after each step of the address arithmetic instead of before.
Return the base register used from tcg_out_tlb_load, so as to
keep that register choice localized to that function.
Reported-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20221023233337.2846860-1-richard.henderson@linaro.org>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv')
0 files changed, 0 insertions, 0 deletions