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| author | Sergey Matyukevich <sergey.matyukevich@syntacore.com> | 2023-01-31 20:09:55 +0300 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2023-02-07 08:19:23 +1000 |
| commit | 26934f9a95264221ed8e6d603b8099508fbd2a5e (patch) | |
| tree | 5966712ae7b1754cc85e35162a94cd36186965b8 /hw/riscv | |
| parent | 606a2439babb7d676af32e15232e94159d67bbeb (diff) | |
| download | qemu-26934f9a95264221ed8e6d603b8099508fbd2a5e.zip qemu-26934f9a95264221ed8e6d603b8099508fbd2a5e.tar.gz qemu-26934f9a95264221ed8e6d603b8099508fbd2a5e.tar.bz2 | |
target/riscv: set tval for triggered watchpoints
According to privileged spec, if [sm]tval is written with a nonzero
value when a breakpoint exception occurs, then [sm]tval will contain
the faulting virtual address. Set tval to hit address when breakpoint
exception is triggered by hardware watchpoint.
Signed-off-by: Sergey Matyukevich <sergey.matyukevich@syntacore.com>
Reviewed-by: Bin Meng <bmeng@tinylab.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20230131170955.752743-1-geomatsi@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv')
0 files changed, 0 insertions, 0 deletions