diff options
| author | Alistair Francis <alistair.francis@wdc.com> | 2018-07-16 15:30:32 -0700 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2018-07-19 09:05:48 -0700 |
| commit | 4eea9d7deb2332c9010ddea9dcd8680adad1bfed (patch) | |
| tree | e3a103588d60f8cfcca12507bef8dd9eed51f548 /hw/riscv | |
| parent | 54f3141a589caf872f148fdb12c59ad79083f268 (diff) | |
| download | qemu-4eea9d7deb2332c9010ddea9dcd8680adad1bfed.zip qemu-4eea9d7deb2332c9010ddea9dcd8680adad1bfed.tar.gz qemu-4eea9d7deb2332c9010ddea9dcd8680adad1bfed.tar.bz2 | |
sifive_u: Fix crash when introspecting the device
Use the new object_initialize_child() and sysbus_init_child_obj() to
fix the issue.
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Suggested-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Michael Clark <mjc@sifive.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/sifive_u.c | 15 |
1 files changed, 7 insertions, 8 deletions
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 3a6ffeb..59ae1ce 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -244,9 +244,9 @@ static void riscv_sifive_u_init(MachineState *machine) int i; /* Initialize SoC */ - object_initialize(&s->soc, sizeof(s->soc), TYPE_RISCV_U_SOC); - object_property_add_child(OBJECT(machine), "soc", OBJECT(&s->soc), - &error_abort); + object_initialize_child(OBJECT(machine), "soc", &s->soc, + sizeof(s->soc), TYPE_RISCV_U_SOC, + &error_abort, NULL); object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_abort); @@ -303,16 +303,15 @@ static void riscv_sifive_u_soc_init(Object *obj) { SiFiveUSoCState *s = RISCV_U_SOC(obj); - object_initialize(&s->cpus, sizeof(s->cpus), TYPE_RISCV_HART_ARRAY); - object_property_add_child(obj, "cpus", OBJECT(&s->cpus), - &error_abort); + object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus), + TYPE_RISCV_HART_ARRAY, &error_abort, NULL); object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type", &error_abort); object_property_set_int(OBJECT(&s->cpus), smp_cpus, "num-harts", &error_abort); - object_initialize(&s->gem, sizeof(s->gem), TYPE_CADENCE_GEM); - qdev_set_parent_bus(DEVICE(&s->gem), sysbus_get_default()); + sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), + TYPE_CADENCE_GEM); } static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) |