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| author | Alistair Francis <alistair.francis@wdc.com> | 2021-07-09 13:38:39 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2021-07-15 08:56:00 +1000 |
| commit | 5ee257649f1a69d952c56f0a7084653e51971ce5 (patch) | |
| tree | bcb8fb59dc8a9ce9858119cec1a1b3674778f8d8 /hw/riscv | |
| parent | 24bfb98d0642aa7c5e8564750de34448f2f39ec5 (diff) | |
| download | qemu-5ee257649f1a69d952c56f0a7084653e51971ce5.zip qemu-5ee257649f1a69d952c56f0a7084653e51971ce5.tar.gz qemu-5ee257649f1a69d952c56f0a7084653e51971ce5.tar.bz2 | |
hw/riscv: opentitan: Add the unimplement rv_core_ibex_peri
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-id: ed707782e84118e1b06a32fd79b70fecfb54ff82.1625801868.git.alistair.francis@wdc.com
Diffstat (limited to 'hw/riscv')
| -rw-r--r-- | hw/riscv/opentitan.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index c5a7e3b..933c211 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -58,6 +58,7 @@ static const MemMapEntry ibex_memmap[] = { [IBEX_DEV_ALERT_HANDLER] = { 0x411b0000, 0x1000 }, [IBEX_DEV_NMI_GEN] = { 0x411c0000, 0x1000 }, [IBEX_DEV_OTBN] = { 0x411d0000, 0x10000 }, + [IBEX_DEV_PERI] = { 0x411f0000, 0x10000 }, }; static void opentitan_board_init(MachineState *machine) @@ -217,6 +218,8 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size); create_unimplemented_device("riscv.lowrisc.ibex.otbn", memmap[IBEX_DEV_OTBN].base, memmap[IBEX_DEV_OTBN].size); + create_unimplemented_device("riscv.lowrisc.ibex.peri", + memmap[IBEX_DEV_PERI].base, memmap[IBEX_DEV_PERI].size); } static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data) |