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| author | Bin Meng <bin.meng@windriver.com> | 2020-09-03 18:40:17 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:19 -0700 |
| commit | 84fcf3c15111de9f0c72efbb6bc0def264555c46 (patch) | |
| tree | 57567c453d5ea85f06f0c753aefa4fa0d9709eae /hw/riscv/virt.c | |
| parent | 406fafd5d0f9a1c6a365ff1733c26a043b1c4877 (diff) | |
| download | qemu-84fcf3c15111de9f0c72efbb6bc0def264555c46.zip qemu-84fcf3c15111de9f0c72efbb6bc0def264555c46.tar.gz qemu-84fcf3c15111de9f0c72efbb6bc0def264555c46.tar.bz2 | |
hw/riscv: Move sifive_plic model to hw/intc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_plic model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-7-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/virt.c')
| -rw-r--r-- | hw/riscv/virt.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index bce2020..0caab8e 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -30,12 +30,12 @@ #include "hw/char/serial.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" -#include "hw/riscv/sifive_plic.h" #include "hw/riscv/sifive_test.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" #include "hw/intc/sifive_clint.h" +#include "hw/intc/sifive_plic.h" #include "chardev/char.h" #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" |