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| author | Bin Meng <bin.meng@windriver.com> | 2020-09-03 18:40:18 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:19 -0700 |
| commit | 70eb9f9cd1c0b519b31df8ab08ee2198b0e16176 (patch) | |
| tree | edda50d2ae4666242c391c913f473118749e6919 /hw/riscv/spike.c | |
| parent | 84fcf3c15111de9f0c72efbb6bc0def264555c46 (diff) | |
| download | qemu-70eb9f9cd1c0b519b31df8ab08ee2198b0e16176.zip qemu-70eb9f9cd1c0b519b31df8ab08ee2198b0e16176.tar.gz qemu-70eb9f9cd1c0b519b31df8ab08ee2198b0e16176.tar.bz2 | |
hw/riscv: Move riscv_htif model to hw/char
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move riscv_htif model to hw/char directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-8-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/spike.c')
| -rw-r--r-- | hw/riscv/spike.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 59d9d87..3fd152a 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -31,11 +31,11 @@ #include "hw/loader.h" #include "hw/sysbus.h" #include "target/riscv/cpu.h" -#include "hw/riscv/riscv_htif.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/spike.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" +#include "hw/char/riscv_htif.h" #include "hw/intc/sifive_clint.h" #include "chardev/char.h" #include "sysemu/arch_init.h" |