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author | Alistair Francis <alistair.francis@wdc.com> | 2022-01-06 07:39:36 +1000 |
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committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-08 15:46:09 +1000 |
commit | 8f972e5b4beeeb35b15f75499d18a8cc5a320ce7 (patch) | |
tree | c161e5404d32d11b76b14461aa6da554d2a5bde6 /hw/riscv/sifive_u.c | |
parent | 07cb270a9ac914431577321b0e3e99d79cf56254 (diff) | |
download | qemu-8f972e5b4beeeb35b15f75499d18a8cc5a320ce7.zip qemu-8f972e5b4beeeb35b15f75499d18a8cc5a320ce7.tar.gz qemu-8f972e5b4beeeb35b15f75499d18a8cc5a320ce7.tar.bz2 |
hw/riscv: Use error_fatal for SoC realisation
When realising the SoC use error_fatal instead of error_abort as the
process can fail and report useful information to the user.
Currently a user can see this:
$ ../qemu/bld/qemu-system-riscv64 -M sifive_u -S -monitor stdio -display none -drive if=pflash
QEMU 6.1.93 monitor - type 'help' for more information
(qemu) Unexpected error in sifive_u_otp_realize() at ../hw/misc/sifive_u_otp.c:229:
qemu-system-riscv64: OTP drive size < 16K
Aborted (core dumped)
Which this patch addresses
Reported-by: Markus Armbruster <armbru@redhat.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220105213937.1113508-8-alistair.francis@opensource.wdc.com>
Diffstat (limited to 'hw/riscv/sifive_u.c')
-rw-r--r-- | hw/riscv/sifive_u.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index aa74e67..7fbc7de 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -547,7 +547,7 @@ static void sifive_u_machine_init(MachineState *machine) &error_abort); object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, &error_abort); - qdev_realize(DEVICE(&s->soc), NULL, &error_abort); + qdev_realize(DEVICE(&s->soc), NULL, &error_fatal); /* register RAM */ memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base, |