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| author | Peter Maydell <peter.maydell@linaro.org> | 2018-04-20 15:52:43 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2018-04-26 13:57:00 +0100 |
| commit | 9bca0edb282de0007a4f068d9d20f3e3c3aadef7 (patch) | |
| tree | 98d47ad92ff728cec3b2ac52812f15141226789c /hw/riscv/sifive_e.c | |
| parent | a8d78cd0ab6204b6ee8897e30d0fbb9c8979ddca (diff) | |
| download | qemu-9bca0edb282de0007a4f068d9d20f3e3c3aadef7.zip qemu-9bca0edb282de0007a4f068d9d20f3e3c3aadef7.tar.gz qemu-9bca0edb282de0007a4f068d9d20f3e3c3aadef7.tar.bz2 | |
Change references to serial_hds[] to serial_hd()
Change all the uses of serial_hds[] to go via the new
serial_hd() function. Code change produced with:
find hw -name '*.[ch]' | xargs sed -i -e 's/serial_hds\[\([^]]*\)\]/serial_hd(\1)/g'
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-id: 20180420145249.32435-8-peter.maydell@linaro.org
Diffstat (limited to 'hw/riscv/sifive_e.c')
| -rw-r--r-- | hw/riscv/sifive_e.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 19eca36..4872448 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -162,13 +162,13 @@ static void riscv_sifive_e_init(MachineState *machine) sifive_mmio_emulate(sys_mem, "riscv.sifive.e.gpio0", memmap[SIFIVE_E_GPIO0].base, memmap[SIFIVE_E_GPIO0].size); sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base, - serial_hds[0], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART0_IRQ]); + serial_hd(0), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART0_IRQ]); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0", memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0", memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size); /* sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, - serial_hds[1], SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART1_IRQ]); */ + serial_hd(1), SIFIVE_PLIC(s->plic)->irqs[SIFIVE_E_UART1_IRQ]); */ sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1", memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1", |