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authorAlistair Francis <alistair.francis@wdc.com>2020-05-13 10:42:46 -0700
committerAlistair Francis <alistair.francis@wdc.com>2020-06-19 08:24:07 -0700
commit5a842062b9d0ffc27ebfc6d4ce0a80a95c6055b1 (patch)
treecf6ea7f11f5f0aafdc450287a2e4cbfc14acc1aa /hw/riscv/sifive_e.c
parent354908cee1f7ff761b5fedbdb6376c378c10f941 (diff)
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sifive_e: Support the revB machine
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/sifive_e.c')
-rw-r--r--hw/riscv/sifive_e.c34
1 files changed, 30 insertions, 4 deletions
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 1c17d02..36486b7 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -95,10 +95,14 @@ static void riscv_sifive_e_init(MachineState *machine)
memmap[SIFIVE_E_DTIM].base, main_mem);
/* Mask ROM reset vector */
- uint32_t reset_vec[2] = {
- 0x204002b7, /* 0x1000: lui t0,0x20400 */
- 0x00028067, /* 0x1004: jr t0 */
- };
+ uint32_t reset_vec[2];
+
+ if (s->revb) {
+ reset_vec[0] = 0x200102b7; /* 0x1000: lui t0,0x20010 */
+ } else {
+ reset_vec[0] = 0x204002b7; /* 0x1000: lui t0,0x20400 */
+ }
+ reset_vec[1] = 0x00028067; /* 0x1004: jr t0 */
/* copy in the reset vector in little_endian byte order */
for (i = 0; i < sizeof(reset_vec) >> 2; i++) {
@@ -112,8 +116,30 @@ static void riscv_sifive_e_init(MachineState *machine)
}
}
+static bool sifive_e_machine_get_revb(Object *obj, Error **errp)
+{
+ SiFiveEState *s = RISCV_E_MACHINE(obj);
+
+ return s->revb;
+}
+
+static void sifive_e_machine_set_revb(Object *obj, bool value, Error **errp)
+{
+ SiFiveEState *s = RISCV_E_MACHINE(obj);
+
+ s->revb = value;
+}
+
static void sifive_e_machine_instance_init(Object *obj)
{
+ SiFiveEState *s = RISCV_E_MACHINE(obj);
+
+ s->revb = false;
+ object_property_add_bool(obj, "revb", sifive_e_machine_get_revb,
+ sifive_e_machine_set_revb);
+ object_property_set_description(obj, "revb",
+ "Set on to tell QEMU that it should model "
+ "the revB HiFive1 board");
}
static void sifive_e_machine_class_init(ObjectClass *oc, void *data)