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| author | Wilfred Mallawa <wilfred.mallawa@wdc.com> | 2022-01-10 15:16:06 +1000 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2022-01-21 15:52:56 +1000 |
| commit | 28ca4689ae94a27a6a337546425cda30d0e885c3 (patch) | |
| tree | f94b86e92e91f720651dd549a335d33167791616 /hw/riscv/opentitan.c | |
| parent | 2c89b5af5e72ab8c9d544c6e30399528b2238827 (diff) | |
| download | qemu-28ca4689ae94a27a6a337546425cda30d0e885c3.zip qemu-28ca4689ae94a27a6a337546425cda30d0e885c3.tar.gz qemu-28ca4689ae94a27a6a337546425cda30d0e885c3.tar.bz2 | |
hw: timer: ibex_timer: Fixup reading w/o register
This change fixes a bug where a write only register is read.
As per https://docs.opentitan.org/hw/ip/rv_timer/doc/#register-table
the 'INTR_TEST0' register is write only.
Signed-off-by: Wilfred Mallawa <wilfred.mallawa@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20220110051606.4031241-1-alistair.francis@opensource.wdc.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/opentitan.c')
0 files changed, 0 insertions, 0 deletions