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author | Marc-André Lureau <marcandre.lureau@redhat.com> | 2019-08-17 13:55:58 +0400 |
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committer | Paolo Bonzini <pbonzini@redhat.com> | 2020-08-21 06:30:33 -0400 |
commit | 2c44220d055d12142f27cf513848f17d6007ae35 (patch) | |
tree | 72593b21d3f6e20a325be46bfc05b69457e14244 /hw/riscv/meson.build | |
parent | b2c00bce54cce0dbb8c7fd3dd397cfdaca4c28ef (diff) | |
download | qemu-2c44220d055d12142f27cf513848f17d6007ae35.zip qemu-2c44220d055d12142f27cf513848f17d6007ae35.tar.gz qemu-2c44220d055d12142f27cf513848f17d6007ae35.tar.bz2 |
meson: convert hw/arch*
Each architecture's sourceset is placed in an hw_arch dictionary, and picked up
from there when building the per-emulator static_library.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Diffstat (limited to 'hw/riscv/meson.build')
-rw-r--r-- | hw/riscv/meson.build | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build new file mode 100644 index 0000000..2de8e5a --- /dev/null +++ b/hw/riscv/meson.build @@ -0,0 +1,19 @@ +riscv_ss = ss.source_set() +riscv_ss.add(files('boot.c')) +riscv_ss.add(when: 'CONFIG_HART', if_true: files('riscv_hart.c')) +riscv_ss.add(when: 'CONFIG_OPENTITAN', if_true: files('opentitan.c')) +riscv_ss.add(when: 'CONFIG_RISCV_VIRT', if_true: files('virt.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_clint.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_gpio.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_plic.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e_prci.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c')) +riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_prci.c')) +riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c')) +riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) + +hw_arch += {'riscv': riscv_ss} |