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| author | Bin Meng <bin.meng@windriver.com> | 2020-09-03 18:40:14 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:19 -0700 |
| commit | 0fa9e329454aaccc6dbb6a4f52ad0c88a060a3b6 (patch) | |
| tree | 2e1a7c7e45eff69893f38bc9cb7448385b5a21b9 /hw/riscv/meson.build | |
| parent | 9fe640a53dd8ef33d32ab6e833fa9b6d1356cfae (diff) | |
| download | qemu-0fa9e329454aaccc6dbb6a4f52ad0c88a060a3b6.zip qemu-0fa9e329454aaccc6dbb6a4f52ad0c88a060a3b6.tar.gz qemu-0fa9e329454aaccc6dbb6a4f52ad0c88a060a3b6.tar.bz2 | |
hw/riscv: Move sifive_u_otp model to hw/misc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_u_otp model to hw/misc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-4-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/meson.build')
| -rw-r--r-- | hw/riscv/meson.build | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index 3462cb5..74a73b2 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -11,7 +11,6 @@ riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_test.c')) riscv_ss.add(when: 'CONFIG_SIFIVE', if_true: files('sifive_uart.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_E', if_true: files('sifive_e.c')) riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) -riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u_otp.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('riscv_htif.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c')) |