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authorAlistair Francis <alistair.francis@wdc.com>2020-10-13 17:17:30 -0700
committerAlistair Francis <alistair.francis@wdc.com>2020-10-22 12:00:22 -0700
commitc40778429157afbd9ba2236f1e06ca24d980cdfe (patch)
tree829c5ce5d1e946aff959ee1579a7fc0d92c56281 /hw/riscv/boot.c
parente66c531e13f8ba3d8b7f32719f7964ba1b185a23 (diff)
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hw/riscv: Add a riscv_is_32_bit() function
Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Palmer Dabbelt <palmerdabbelt@google.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com> Message-id: 4c6a85dfb6dd470aa79356ebc1b02f479c2758e0.1602634524.git.alistair.francis@wdc.com
Diffstat (limited to 'hw/riscv/boot.c')
-rw-r--r--hw/riscv/boot.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index fa69930..5dea644 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -40,6 +40,15 @@
#define fw_dynamic_info_data(__val) cpu_to_le64(__val)
#endif
+bool riscv_is_32_bit(MachineState *machine)
+{
+ if (!strncmp(machine->cpu_type, "rv32", 4)) {
+ return true;
+ } else {
+ return false;
+ }
+}
+
target_ulong riscv_find_and_load_firmware(MachineState *machine,
const char *default_machine_firmware,
hwaddr firmware_load_addr,