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| author | Bin Meng <bin.meng@windriver.com> | 2020-09-03 18:40:15 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:19 -0700 |
| commit | 4921a0ce86cecd03e6918832673db79de62e6fe1 (patch) | |
| tree | 5da8decc3b08809b7f5fdaddedb25d5e43fd8166 /hw/riscv/Kconfig | |
| parent | 0fa9e329454aaccc6dbb6a4f52ad0c88a060a3b6 (diff) | |
| download | qemu-4921a0ce86cecd03e6918832673db79de62e6fe1.zip qemu-4921a0ce86cecd03e6918832673db79de62e6fe1.tar.gz qemu-4921a0ce86cecd03e6918832673db79de62e6fe1.tar.bz2 | |
hw/riscv: Move sifive_gpio model to hw/gpio
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_gpio model to hw/gpio directory.
Note this also removes the trace-events in the hw/riscv directory,
since gpio is the only supported trace target in that directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-5-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/Kconfig')
| -rw-r--r-- | hw/riscv/Kconfig | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 76eaf77..5a8335b 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -15,6 +15,7 @@ config SIFIVE_E bool select HART select SIFIVE + select SIFIVE_GPIO select SIFIVE_E_PRCI select UNIMP @@ -23,6 +24,7 @@ config SIFIVE_U select CADENCE select HART select SIFIVE + select SIFIVE_GPIO select SIFIVE_PDMA select SIFIVE_U_OTP select SIFIVE_U_PRCI |