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| author | Bin Meng <bin.meng@windriver.com> | 2020-10-28 13:30:03 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-11-03 07:17:23 -0800 |
| commit | 933f73f13e5ceb9357e9c9d51ce39c43aa1d534f (patch) | |
| tree | 1276d3fe98992197dd292cca037981e77fe6c78a /hw/riscv/Kconfig | |
| parent | 3400b15bbe0fbc672fee9a18268154b07a1fed2e (diff) | |
| download | qemu-933f73f13e5ceb9357e9c9d51ce39c43aa1d534f.zip qemu-933f73f13e5ceb9357e9c9d51ce39c43aa1d534f.tar.gz qemu-933f73f13e5ceb9357e9c9d51ce39c43aa1d534f.tar.bz2 | |
hw/riscv: microchip_pfsoc: Connect DDR memory controller modules
Connect DDR SGMII PHY module and CFG module to the PolarFire SoC.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-id: 1603863010-15807-4-git-send-email-bmeng.cn@gmail.com
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/Kconfig')
| -rw-r--r-- | hw/riscv/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 2df978f..c8e50bd 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -4,6 +4,7 @@ config IBEX config MICROCHIP_PFSOC bool select CADENCE_SDHCI + select MCHP_PFSOC_DMC select MCHP_PFSOC_MMUART select MSI_NONBROKEN select SIFIVE_CLINT |