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| author | Bin Meng <bin.meng@windriver.com> | 2020-09-03 18:40:16 +0800 |
|---|---|---|
| committer | Alistair Francis <alistair.francis@wdc.com> | 2020-09-09 15:54:19 -0700 |
| commit | 406fafd5d0f9a1c6a365ff1733c26a043b1c4877 (patch) | |
| tree | ee4ed77217e62a3d3a8c185e8eda59ff2a138c35 /hw/riscv/Kconfig | |
| parent | 4921a0ce86cecd03e6918832673db79de62e6fe1 (diff) | |
| download | qemu-406fafd5d0f9a1c6a365ff1733c26a043b1c4877.zip qemu-406fafd5d0f9a1c6a365ff1733c26a043b1c4877.tar.gz qemu-406fafd5d0f9a1c6a365ff1733c26a043b1c4877.tar.bz2 | |
hw/riscv: Move sifive_clint model to hw/intc
This is an effort to clean up the hw/riscv directory. Ideally it
should only contain the RISC-V SoC / machine codes plus generic
codes. Let's move sifive_clint model to hw/intc directory.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <1599129623-68957-6-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Diffstat (limited to 'hw/riscv/Kconfig')
| -rw-r--r-- | hw/riscv/Kconfig | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 5a8335b..f8bb7e7 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -15,6 +15,7 @@ config SIFIVE_E bool select HART select SIFIVE + select SIFIVE_CLINT select SIFIVE_GPIO select SIFIVE_E_PRCI select UNIMP @@ -24,6 +25,7 @@ config SIFIVE_U select CADENCE select HART select SIFIVE + select SIFIVE_CLINT select SIFIVE_GPIO select SIFIVE_PDMA select SIFIVE_U_OTP @@ -35,6 +37,7 @@ config SPIKE select HART select HTIF select SIFIVE + select SIFIVE_CLINT config OPENTITAN bool @@ -54,11 +57,13 @@ config RISCV_VIRT select PCI_EXPRESS_GENERIC_BRIDGE select PFLASH_CFI01 select SIFIVE + select SIFIVE_CLINT config MICROCHIP_PFSOC bool select HART select SIFIVE + select SIFIVE_CLINT select UNIMP select MCHP_PFSOC_MMUART select SIFIVE_PDMA |