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authorDmitry Eremin-Solenikov <dbaryshkov@gmail.com>2011-02-25 12:13:38 +0100
committerAndrzej Zaborowski <balrog@zabor.org>2011-02-25 12:13:38 +0100
commite1f8c729fa890c67bb4532f22c22ace6fb0e1aaf (patch)
tree71a7936f73ce841cc41dbd90457ab87044c9fdbc /hw/pxa2xx_gpio.c
parent3e1dbc3bd40338f19a2469feabd5f1dc5a4f5a9d (diff)
downloadqemu-e1f8c729fa890c67bb4532f22c22ace6fb0e1aaf.zip
qemu-e1f8c729fa890c67bb4532f22c22ace6fb0e1aaf.tar.gz
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pxa2xx_pic: update to use qdev
Use qdev/sysbus framework to handle pxa2xx-pic. Instead of exposing IRQs via array, reference them via qdev_get_gpio_in(). Patch has been modified by the committer. Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
Diffstat (limited to 'hw/pxa2xx_gpio.c')
-rw-r--r--hw/pxa2xx_gpio.c11
1 files changed, 7 insertions, 4 deletions
diff --git a/hw/pxa2xx_gpio.c b/hw/pxa2xx_gpio.c
index 789965d..200b0cf 100644
--- a/hw/pxa2xx_gpio.c
+++ b/hw/pxa2xx_gpio.c
@@ -253,7 +253,7 @@ static CPUWriteMemoryFunc * const pxa2xx_gpio_writefn[] = {
};
DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
- CPUState *env, qemu_irq *pic, int lines)
+ CPUState *env, DeviceState *pic, int lines)
{
DeviceState *dev;
@@ -263,9 +263,12 @@ DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
qdev_init_nofail(dev);
sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
- sysbus_connect_irq(sysbus_from_qdev(dev), 0, pic[PXA2XX_PIC_GPIO_0]);
- sysbus_connect_irq(sysbus_from_qdev(dev), 1, pic[PXA2XX_PIC_GPIO_1]);
- sysbus_connect_irq(sysbus_from_qdev(dev), 2, pic[PXA2XX_PIC_GPIO_X]);
+ sysbus_connect_irq(sysbus_from_qdev(dev), 0,
+ qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
+ sysbus_connect_irq(sysbus_from_qdev(dev), 1,
+ qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
+ sysbus_connect_irq(sysbus_from_qdev(dev), 2,
+ qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
return dev;
}