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authorpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2007-11-11 00:04:49 +0000
committerpbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>2007-11-11 00:04:49 +0000
commit9ee6e8bb853bdea7ef6c645a1a07aa55fd206aba (patch)
tree1cd430d3d9ac641c8550cfd8956dbcce1a4b9121 /hw/pxa2xx.c
parentee4e83ed8ddc8dac572a0123398adf78b63014ae (diff)
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ARMv7 support.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3572 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/pxa2xx.c')
-rw-r--r--hw/pxa2xx.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c
index ebaff13..3c10839 100644
--- a/hw/pxa2xx.c
+++ b/hw/pxa2xx.c
@@ -297,7 +297,7 @@ static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm,
ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I;
s->env->cp15.c1_sys = 0;
s->env->cp15.c1_coproc = 0;
- s->env->cp15.c2_base = 0;
+ s->env->cp15.c2_base0 = 0;
s->env->cp15.c3 = 0;
s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */
s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */
@@ -2031,7 +2031,8 @@ struct pxa2xx_state_s *pxa270_init(unsigned int sdram_size,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
- register_savevm("cpu", 0, 0, cpu_save, cpu_load, s->env);
+ register_savevm("cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load,
+ s->env);
/* SDRAM & Internal Memory Storage */
cpu_register_physical_memory(PXA2XX_SDRAM_BASE,
@@ -2145,7 +2146,8 @@ struct pxa2xx_state_s *pxa255_init(unsigned int sdram_size,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
- register_savevm("cpu", 0, 0, cpu_save, cpu_load, s->env);
+ register_savevm("cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load,
+ s->env);
/* SDRAM & Internal Memory Storage */
cpu_register_physical_memory(PXA2XX_SDRAM_BASE, sdram_size,