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| author | Alexander Graf <agraf@suse.de> | 2010-12-08 12:05:40 +0100 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2010-12-11 15:24:25 +0000 |
| commit | 6ebf5905f4a664a873cf7f49094960f08cb3a2d5 (patch) | |
| tree | 4491565c563b2d3d60dc97e895b30278cb16300e /hw/ppce500_pci.c | |
| parent | 0f4f039b9895e2e52d591a123017cb53fe636f9d (diff) | |
| download | qemu-6ebf5905f4a664a873cf7f49094960f08cb3a2d5.zip qemu-6ebf5905f4a664a873cf7f49094960f08cb3a2d5.tar.gz qemu-6ebf5905f4a664a873cf7f49094960f08cb3a2d5.tar.bz2 | |
pci-host: Delegate bswap to mmio layer
The only reason we have bswap versions of the pci host code is that
most pci host devices are little endian. The ppc e500 is the only
odd one here, being big endian.
So let's directly pass the endianness down to the mmio layer and not
worry about it on the pci host layer.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'hw/ppce500_pci.c')
| -rw-r--r-- | hw/ppce500_pci.c | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c index 71302ba..11edd03 100644 --- a/hw/ppce500_pci.c +++ b/hw/ppce500_pci.c @@ -292,13 +292,15 @@ PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers) controller->pci_dev = d; /* CFGADDR */ - index = pci_host_conf_register_mmio(&controller->pci_state, 0); + index = pci_host_conf_register_mmio(&controller->pci_state, + DEVICE_BIG_ENDIAN); if (index < 0) goto free; cpu_register_physical_memory(registers + PCIE500_CFGADDR, 4, index); /* CFGDATA */ - index = pci_host_data_register_mmio(&controller->pci_state, 0); + index = pci_host_data_register_mmio(&controller->pci_state, + DEVICE_BIG_ENDIAN); if (index < 0) goto free; cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index); |