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| author | Alexander Graf <agraf@suse.de> | 2010-12-08 12:05:37 +0100 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2010-12-11 15:24:25 +0000 |
| commit | 2507c12ab026b2286b0a47035c629f3d568c96f4 (patch) | |
| tree | 949765d6112d70536a3806eb822798a0e04577da /hw/ppce500_pci.c | |
| parent | dd310534e3bf8045096654df41471fd7132887b2 (diff) | |
| download | qemu-2507c12ab026b2286b0a47035c629f3d568c96f4.zip qemu-2507c12ab026b2286b0a47035c629f3d568c96f4.tar.gz qemu-2507c12ab026b2286b0a47035c629f3d568c96f4.tar.bz2 | |
Add endianness as io mem parameter
As stated before, devices can be little, big or native endian. The
target endianness is not of their concern, so we need to push things
down a level.
This patch adds a parameter to cpu_register_io_memory that allows a
device to choose its endianness. For now, all devices simply choose
native endian, because that's the same behavior as before.
Signed-off-by: Alexander Graf <agraf@suse.de>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'hw/ppce500_pci.c')
| -rw-r--r-- | hw/ppce500_pci.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/ppce500_pci.c b/hw/ppce500_pci.c index 8ac99f2..71302ba 100644 --- a/hw/ppce500_pci.c +++ b/hw/ppce500_pci.c @@ -304,7 +304,8 @@ PCIBus *ppce500_pci_init(qemu_irq pci_irqs[4], target_phys_addr_t registers) cpu_register_physical_memory(registers + PCIE500_CFGDATA, 4, index); index = cpu_register_io_memory(e500_pci_reg_read, - e500_pci_reg_write, controller); + e500_pci_reg_write, controller, + DEVICE_NATIVE_ENDIAN); if (index < 0) goto free; cpu_register_physical_memory(registers + PCIE500_REG_BASE, |