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authorGreg Kurz <groug@kaod.org>2019-12-13 13:00:35 +0100
committerDavid Gibson <david@gibson.dropbear.id.au>2019-12-17 10:59:11 +1100
commit70c059e9266fc7d79e40c9d297722ccb717ec386 (patch)
tree34d3199b03255b0dd1455282099d36284e1de8ab /hw/ppc
parent3caf7bd0a2874717c5cf052a9840efe9c7774f2e (diff)
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ppc/pnv: Introduce PnvChipClass::xscom_pcba() method
The XSCOM bus is implemented with a QOM interface, which is mostly generic from a CPU type standpoint, except for the computation of addresses on the Pervasive Connect Bus (PCB) network. This is handled by the pnv_xscom_pcba() function with a switch statement based on the chip_type class level attribute of the CPU chip. This can be achieved using QOM. Also the address argument is masked with PNV_XSCOM_SIZE - 1, which is for POWER8 only. Addresses may have different sizes with other CPU types. Have each CPU chip type handle the appropriate computation with a QOM xscom_pcba() method. Signed-off-by: Greg Kurz <groug@kaod.org> Message-Id: <157623843543.360005.13996472463887521794.stgit@bahia.lan> Reviewed-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/ppc')
-rw-r--r--hw/ppc/pnv.c23
-rw-r--r--hw/ppc/pnv_xscom.c14
2 files changed, 24 insertions, 13 deletions
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index b338803..41e5d76 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -1120,6 +1120,12 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
&chip8->homer.regs);
}
+static uint32_t pnv_chip_power8_xscom_pcba(PnvChip *chip, uint64_t addr)
+{
+ addr &= (PNV_XSCOM_SIZE - 1);
+ return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
+}
+
static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -1137,6 +1143,7 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
k->dt_populate = pnv_chip_power8_dt_populate;
k->pic_print_info = pnv_chip_power8_pic_print_info;
k->xscom_core_base = pnv_chip_power8_xscom_core_base;
+ k->xscom_pcba = pnv_chip_power8_xscom_pcba;
dc->desc = "PowerNV Chip POWER8E";
device_class_set_parent_realize(dc, pnv_chip_power8_realize,
@@ -1160,6 +1167,7 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
k->dt_populate = pnv_chip_power8_dt_populate;
k->pic_print_info = pnv_chip_power8_pic_print_info;
k->xscom_core_base = pnv_chip_power8_xscom_core_base;
+ k->xscom_pcba = pnv_chip_power8_xscom_pcba;
dc->desc = "PowerNV Chip POWER8";
device_class_set_parent_realize(dc, pnv_chip_power8_realize,
@@ -1183,6 +1191,7 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
k->dt_populate = pnv_chip_power8_dt_populate;
k->pic_print_info = pnv_chip_power8_pic_print_info;
k->xscom_core_base = pnv_chip_power8_xscom_core_base;
+ k->xscom_pcba = pnv_chip_power8_xscom_pcba;
dc->desc = "PowerNV Chip POWER8NVL";
device_class_set_parent_realize(dc, pnv_chip_power8_realize,
@@ -1339,6 +1348,12 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
&chip9->homer.regs);
}
+static uint32_t pnv_chip_power9_xscom_pcba(PnvChip *chip, uint64_t addr)
+{
+ addr &= (PNV9_XSCOM_SIZE - 1);
+ return addr >> 3;
+}
+
static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -1356,6 +1371,7 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
k->dt_populate = pnv_chip_power9_dt_populate;
k->pic_print_info = pnv_chip_power9_pic_print_info;
k->xscom_core_base = pnv_chip_power9_xscom_core_base;
+ k->xscom_pcba = pnv_chip_power9_xscom_pcba;
dc->desc = "PowerNV Chip POWER9";
device_class_set_parent_realize(dc, pnv_chip_power9_realize,
@@ -1421,6 +1437,12 @@ static void pnv_chip_power10_realize(DeviceState *dev, Error **errp)
(uint64_t) PNV10_LPCM_BASE(chip));
}
+static uint32_t pnv_chip_power10_xscom_pcba(PnvChip *chip, uint64_t addr)
+{
+ addr &= (PNV10_XSCOM_SIZE - 1);
+ return addr >> 3;
+}
+
static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
@@ -1438,6 +1460,7 @@ static void pnv_chip_power10_class_init(ObjectClass *klass, void *data)
k->dt_populate = pnv_chip_power10_dt_populate;
k->pic_print_info = pnv_chip_power10_pic_print_info;
k->xscom_core_base = pnv_chip_power10_xscom_core_base;
+ k->xscom_pcba = pnv_chip_power10_xscom_pcba;
dc->desc = "PowerNV Chip POWER10";
device_class_set_parent_realize(dc, pnv_chip_power10_realize,
diff --git a/hw/ppc/pnv_xscom.c b/hw/ppc/pnv_xscom.c
index 5ae9dfb..b681c72 100644
--- a/hw/ppc/pnv_xscom.c
+++ b/hw/ppc/pnv_xscom.c
@@ -57,19 +57,7 @@ static void xscom_complete(CPUState *cs, uint64_t hmer_bits)
static uint32_t pnv_xscom_pcba(PnvChip *chip, uint64_t addr)
{
- addr &= (PNV_XSCOM_SIZE - 1);
-
- switch (PNV_CHIP_GET_CLASS(chip)->chip_type) {
- case PNV_CHIP_POWER8E:
- case PNV_CHIP_POWER8:
- case PNV_CHIP_POWER8NVL:
- return ((addr >> 4) & ~0xfull) | ((addr >> 3) & 0xf);
- case PNV_CHIP_POWER9:
- case PNV_CHIP_POWER10:
- return addr >> 3;
- default:
- g_assert_not_reached();
- }
+ return PNV_CHIP_GET_CLASS(chip)->xscom_pcba(chip, addr);
}
static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)