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| author | Nicholas Piggin <npiggin@gmail.com> | 2021-05-01 17:24:35 +1000 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2021-05-04 13:12:46 +1000 |
| commit | 526cdce771fa27c37b68fd235ff9f1caa0bdd563 (patch) | |
| tree | 17ecd66691cbeb0e317e767001362a637200a3d0 /hw/ppc | |
| parent | 8b7e6b07a46809a75b857d30ae47e697e0f9b724 (diff) | |
| download | qemu-526cdce771fa27c37b68fd235ff9f1caa0bdd563.zip qemu-526cdce771fa27c37b68fd235ff9f1caa0bdd563.tar.gz qemu-526cdce771fa27c37b68fd235ff9f1caa0bdd563.tar.bz2 | |
target/ppc: Add POWER10 exception model
POWER10 adds a new bit that modifies interrupt behaviour, LPCR[HAIL],
and it removes support for the LPCR[AIL]=0b10 mode.
Reviewed-by: Cédric Le Goater <clg@kaod.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Message-Id: <20210501072436.145444-3-npiggin@gmail.com>
[dwg: Corrected tab indenting]
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/ppc')
| -rw-r--r-- | hw/ppc/spapr_hcall.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 2fbe04a..7275d0b 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1396,7 +1396,12 @@ static target_ulong h_set_mode_resource_addr_trans_mode(PowerPCCPU *cpu, } if (mflags == 1) { - /* AIL=1 is reserved */ + /* AIL=1 is reserved in POWER8/POWER9/POWER10 */ + return H_UNSUPPORTED_FLAG; + } + + if (mflags == 2 && (pcc->insns_flags2 & PPC2_ISA310)) { + /* AIL=2 is reserved in POWER10 (ISA v3.1) */ return H_UNSUPPORTED_FLAG; } |