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author | Blue Swirl <blauwirbel@gmail.com> | 2009-08-15 14:27:05 +0000 |
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committer | Blue Swirl <blauwirbel@gmail.com> | 2009-08-15 14:27:05 +0000 |
commit | 802670e6c9026c945c232a46bb5c789601334280 (patch) | |
tree | dff18b23828c7fc5c8843f93caab2068c5043e92 /hw/ppc4xx_devs.c | |
parent | 1786dc15eeecdc49a2097e262a9ad1510a14dcc0 (diff) | |
download | qemu-802670e6c9026c945c232a46bb5c789601334280.zip qemu-802670e6c9026c945c232a46bb5c789601334280.tar.gz qemu-802670e6c9026c945c232a46bb5c789601334280.tar.bz2 |
PPC: clean up ppc405
Rely on the subpage system instead of the local version.
Make most functions "static".
Fix wrong parameter passed to ppc4xx_pob_reset.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
Diffstat (limited to 'hw/ppc4xx_devs.c')
-rw-r--r-- | hw/ppc4xx_devs.c | 195 |
1 files changed, 0 insertions, 195 deletions
diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c index 828fbf7..8f8a44c 100644 --- a/hw/ppc4xx_devs.c +++ b/hw/ppc4xx_devs.c @@ -66,201 +66,6 @@ CPUState *ppc4xx_init (const char *cpu_model, } /*****************************************************************************/ -/* Fake device used to map multiple devices in a single memory page */ -#define MMIO_AREA_BITS 8 -#define MMIO_AREA_LEN (1 << MMIO_AREA_BITS) -#define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS)) -#define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1)) -struct ppc4xx_mmio_t { - target_phys_addr_t base; - CPUReadMemoryFunc **mem_read[MMIO_AREA_NB]; - CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB]; - void *opaque[MMIO_AREA_NB]; -}; - -static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr) -{ -#ifdef DEBUG_UNASSIGNED - ppc4xx_mmio_t *mmio; - - mmio = opaque; - printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n", - addr, mmio->base); -#endif - - return 0; -} - -static void unassigned_mmio_writeb (void *opaque, - target_phys_addr_t addr, uint32_t val) -{ -#ifdef DEBUG_UNASSIGNED - ppc4xx_mmio_t *mmio; - - mmio = opaque; - printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n", - addr, val, mmio->base); -#endif -} - -static CPUReadMemoryFunc *unassigned_mmio_read[3] = { - unassigned_mmio_readb, - unassigned_mmio_readb, - unassigned_mmio_readb, -}; - -static CPUWriteMemoryFunc *unassigned_mmio_write[3] = { - unassigned_mmio_writeb, - unassigned_mmio_writeb, - unassigned_mmio_writeb, -}; - -static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio, - target_phys_addr_t addr, int len) -{ - CPUReadMemoryFunc **mem_read; - uint32_t ret; - int idx; - - idx = MMIO_IDX(addr); -#if defined(DEBUG_MMIO) - printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__, - mmio, len, addr, idx); -#endif - mem_read = mmio->mem_read[idx]; - ret = (*mem_read[len])(mmio->opaque[idx], addr); - - return ret; -} - -static void mmio_writelen (ppc4xx_mmio_t *mmio, - target_phys_addr_t addr, uint32_t value, int len) -{ - CPUWriteMemoryFunc **mem_write; - int idx; - - idx = MMIO_IDX(addr); -#if defined(DEBUG_MMIO) - printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08" PRIx32 "\n", - __func__, mmio, len, addr, idx, value); -#endif - mem_write = mmio->mem_write[idx]; - (*mem_write[len])(mmio->opaque[idx], addr, value); -} - -static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr) -{ -#if defined(DEBUG_MMIO) - printf("%s: addr " PADDRX "\n", __func__, addr); -#endif - - return mmio_readlen(opaque, addr, 0); -} - -static void mmio_writeb (void *opaque, - target_phys_addr_t addr, uint32_t value) -{ -#if defined(DEBUG_MMIO) - printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); -#endif - mmio_writelen(opaque, addr, value, 0); -} - -static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr) -{ -#if defined(DEBUG_MMIO) - printf("%s: addr " PADDRX "\n", __func__, addr); -#endif - - return mmio_readlen(opaque, addr, 1); -} - -static void mmio_writew (void *opaque, - target_phys_addr_t addr, uint32_t value) -{ -#if defined(DEBUG_MMIO) - printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); -#endif - mmio_writelen(opaque, addr, value, 1); -} - -static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr) -{ -#if defined(DEBUG_MMIO) - printf("%s: addr " PADDRX "\n", __func__, addr); -#endif - - return mmio_readlen(opaque, addr, 2); -} - -static void mmio_writel (void *opaque, - target_phys_addr_t addr, uint32_t value) -{ -#if defined(DEBUG_MMIO) - printf("%s: addr " PADDRX " val %08" PRIx32 "\n", __func__, addr, value); -#endif - mmio_writelen(opaque, addr, value, 2); -} - -static CPUReadMemoryFunc *mmio_read[] = { - &mmio_readb, - &mmio_readw, - &mmio_readl, -}; - -static CPUWriteMemoryFunc *mmio_write[] = { - &mmio_writeb, - &mmio_writew, - &mmio_writel, -}; - -int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio, - target_phys_addr_t offset, uint32_t len, - CPUReadMemoryFunc **mem_read, - CPUWriteMemoryFunc **mem_write, void *opaque) -{ - target_phys_addr_t end; - int idx, eidx; - - if ((offset + len) > TARGET_PAGE_SIZE) - return -1; - idx = MMIO_IDX(offset); - end = offset + len - 1; - eidx = MMIO_IDX(end); -#if defined(DEBUG_MMIO) - printf("%s: offset " PADDRX " len %08" PRIx32 " " PADDRX " %d %d\n", - __func__, offset, len, end, idx, eidx); -#endif - for (; idx <= eidx; idx++) { - mmio->mem_read[idx] = mem_read; - mmio->mem_write[idx] = mem_write; - mmio->opaque[idx] = opaque; - } - - return 0; -} - -ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base) -{ - ppc4xx_mmio_t *mmio; - int mmio_memory; - - mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t)); - mmio->base = base; - mmio_memory = cpu_register_io_memory(mmio_read, mmio_write, mmio); -#if defined(DEBUG_MMIO) - printf("%s: base " PADDRX " len %08x %d\n", __func__, - base, TARGET_PAGE_SIZE, mmio_memory); -#endif - cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory); - ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE, - unassigned_mmio_read, unassigned_mmio_write, - mmio); - - return mmio; -} - -/*****************************************************************************/ /* "Universal" Interrupt controller */ enum { DCR_UICSR = 0x000, |