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author | Alexey Kardashevskiy <aik@ozlabs.ru> | 2016-06-01 18:57:35 +1000 |
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committer | David Gibson <david@gibson.dropbear.id.au> | 2016-06-07 10:17:45 +1000 |
commit | b4b6eb771a5c2eec47fd87ea28c499a5aa4b6db2 (patch) | |
tree | e905b54eeafe82609c01e505fb915beb44c34804 /hw/ppc/spapr_pci.c | |
parent | a26fdf393404e96b51bec5db9ed6bd54ab6eab85 (diff) | |
download | qemu-b4b6eb771a5c2eec47fd87ea28c499a5aa4b6db2.zip qemu-b4b6eb771a5c2eec47fd87ea28c499a5aa4b6db2.tar.gz qemu-b4b6eb771a5c2eec47fd87ea28c499a5aa4b6db2.tar.bz2 |
spapr_iommu: Add root memory region
We are going to have multiple DMA windows at different offsets on
a PCI bus. For the sake of migration, we will have as many TCE table
objects pre-created as many windows supported.
So we need a way to map windows dynamically onto a PCI bus
when migration of a table is completed but at this stage a TCE table
object does not have access to a PHB to ask it to map a DMA window
backed by just migrated TCE table.
This adds a "root" memory region (UINT64_MAX long) to the TCE object.
This new region is mapped on a PCI bus with enabled overlapping as
there will be one root MR per TCE table, each of them mapped at 0.
The actual IOMMU memory region is a subregion of the root region and
a TCE table enables/disables this subregion and maps it at
the specific offset inside the root MR which is 1:1 mapping of
a PCI address space.
Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Reviewed-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/ppc/spapr_pci.c')
-rw-r--r-- | hw/ppc/spapr_pci.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 7688ae0..a529eff 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -1470,13 +1470,13 @@ static void spapr_phb_realize(DeviceState *dev, Error **errp) return; } + memory_region_add_subregion_overlap(&sphb->iommu_root, 0, + spapr_tce_get_iommu(tcet), 0); + /* Register default 32bit DMA window */ spapr_tce_table_enable(tcet, SPAPR_TCE_PAGE_SHIFT, sphb->dma_win_addr, nb_table); - memory_region_add_subregion(&sphb->iommu_root, tcet->bus_offset, - spapr_tce_get_iommu(tcet)); - sphb->msi = g_hash_table_new_full(g_int_hash, g_int_equal, g_free, g_free); } |