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| author | BALATON Zoltan <balaton@eik.bme.hu> | 2022-09-24 14:28:00 +0200 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2022-10-17 16:15:09 -0300 |
| commit | 03f7041bfdc45f6c981a83fd2d932bad161769ad (patch) | |
| tree | 0a710980b8cf4a95ef2a1c86d6ea55a9e216cb93 /hw/ppc/ppc440_uc.c | |
| parent | ea74acee988e5849ec5b7aa89edc3e676b66d2c4 (diff) | |
| download | qemu-03f7041bfdc45f6c981a83fd2d932bad161769ad.zip qemu-03f7041bfdc45f6c981a83fd2d932bad161769ad.tar.gz qemu-03f7041bfdc45f6c981a83fd2d932bad161769ad.tar.bz2 | |
ppc440_sdram: Get rid of the init RAM hack
Remove the do_init parameter of ppc440_sdram_init and enable SDRAM
controller from the board. Firmware does this so it may only be needed
when booting with -kernel without firmware but we enable SDRAM
unconditionally to preserve previous behaviour.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Message-Id: <c2eda8f83c82f655aa7821a5a8c9310484bd6a1d.1664021647.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'hw/ppc/ppc440_uc.c')
| -rw-r--r-- | hw/ppc/ppc440_uc.c | 15 |
1 files changed, 9 insertions, 6 deletions
diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index 3fbfe4a..e8bc088 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -16,6 +16,7 @@ #include "qemu/module.h" #include "hw/irq.h" #include "exec/memory.h" +#include "cpu.h" #include "hw/ppc/ppc4xx.h" #include "hw/qdev-properties.h" #include "hw/pci/pci.h" @@ -727,12 +728,11 @@ static void sdram_reset(void *opaque) ppc440_sdram_t *sdram = opaque; sdram->addr = 0; - sdram->mcopt2 = SDRAM_DDR2_MCOPT2_DCEN; + sdram->mcopt2 = 0; } void ppc440_sdram_init(CPUPPCState *env, int nbanks, - Ppc4xxSdramBank *ram_banks, - int do_init) + Ppc4xxSdramBank *ram_banks) { ppc440_sdram_t *sdram; int i; @@ -749,9 +749,6 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks, sdram, &dcr_read_sdram, &dcr_write_sdram); ppc_dcr_register(env, SDRAM0_CFGDATA, sdram, &dcr_read_sdram, &dcr_write_sdram); - if (do_init) { - sdram_map_bcr(sdram); - } ppc_dcr_register(env, SDRAM_R0BAS, sdram, &dcr_read_sdram, &dcr_write_sdram); @@ -773,6 +770,12 @@ void ppc440_sdram_init(CPUPPCState *env, int nbanks, sdram, &dcr_read_sdram, &dcr_write_sdram); } +void ppc440_sdram_enable(CPUPPCState *env) +{ + ppc_dcr_write(env->dcr_env, SDRAM0_CFGADDR, 0x21); + ppc_dcr_write(env->dcr_env, SDRAM0_CFGDATA, 0x08000000); +} + /*****************************************************************************/ /* PLB to AHB bridge */ enum { |