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authorBALATON Zoltan <balaton@eik.bme.hu>2022-09-24 14:28:02 +0200
committerDaniel Henrique Barboza <danielhb413@gmail.com>2022-10-17 16:15:09 -0300
commit1e545fbc88bb5abe21553972a2244f272153476d (patch)
treeb13b4f3243f7a4678fd31cf66dab19266497a952 /hw/ppc/ppc440_bamboo.c
parent3db19f124a14e8029d693dc10e031f3611a119bb (diff)
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ppc4xx_sdram: Rename functions to prevent name clashes
Rename functions to avoid name clashes when moving the DDR2 controller model currently called ppc440_sdram to ppc4xx_devs. This also more clearly shows which function belongs to which model. Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <9c09d10fbf36940ebbe30d7038d69cf3f2e58371.1664021647.git.balaton@eik.bme.hu> Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'hw/ppc/ppc440_bamboo.c')
-rw-r--r--hw/ppc/ppc440_bamboo.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c
index 5c35ba6..56f47e7 100644
--- a/hw/ppc/ppc440_bamboo.c
+++ b/hw/ppc/ppc440_bamboo.c
@@ -204,7 +204,7 @@ static void bamboo_init(MachineState *machine)
/* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */
sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, qdev_get_gpio_in(uicdev, 14));
/* Enable SDRAM memory regions, this should be done by the firmware */
- ppc4xx_sdram_enable(PPC4xx_SDRAM_DDR(dev));
+ ppc4xx_sdram_ddr_enable(PPC4xx_SDRAM_DDR(dev));
/* PCI */
dev = sysbus_create_varargs(TYPE_PPC4xx_PCI_HOST_BRIDGE,