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author | Cédric Le Goater <clg@kaod.org> | 2022-08-17 17:08:22 +0200 |
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committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2022-08-31 14:08:06 -0300 |
commit | 2847eb40891b252e66a178532d26a8f7f91c735e (patch) | |
tree | 078fb37a5fdc0f56d9e596b9170417017be418f2 /hw/ppc/ppc405.h | |
parent | 269fbb5b8ac0506b872ad3df277f23de1856ed15 (diff) | |
download | qemu-2847eb40891b252e66a178532d26a8f7f91c735e.zip qemu-2847eb40891b252e66a178532d26a8f7f91c735e.tar.gz qemu-2847eb40891b252e66a178532d26a8f7f91c735e.tar.bz2 |
ppc/ppc405: QOM'ify OCM
The OCM controller is currently modeled as a simple DCR device with
a couple of memory regions.
Reviewed-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
[balaton: ppc4xx_dcr_register changes]
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <ecb93d2d5993bb7a970365744c7d342d4abcb017.1660746880.git.balaton@eik.bme.hu>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'hw/ppc/ppc405.h')
-rw-r--r-- | hw/ppc/ppc405.h | 16 |
1 files changed, 16 insertions, 0 deletions
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index bcf55e4..a5b493d 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -63,6 +63,21 @@ struct ppc4xx_bd_info_t { uint32_t bi_iic_fast[2]; }; +/* On Chip Memory */ +#define TYPE_PPC405_OCM "ppc405-ocm" +OBJECT_DECLARE_SIMPLE_TYPE(Ppc405OcmState, PPC405_OCM); +struct Ppc405OcmState { + Ppc4xxDcrDeviceState parent_obj; + + MemoryRegion ram; + MemoryRegion isarc_ram; + MemoryRegion dsarc_ram; + uint32_t isarc; + uint32_t isacntl; + uint32_t dsarc; + uint32_t dsacntl; +}; + /* General purpose timers */ #define TYPE_PPC405_GPT "ppc405-gpt" OBJECT_DECLARE_SIMPLE_TYPE(Ppc405GptState, PPC405_GPT); @@ -136,6 +151,7 @@ struct Ppc405SoCState { DeviceState *uic; Ppc405CpcState cpc; Ppc405GptState gpt; + Ppc405OcmState ocm; }; /* PowerPC 405 core */ |