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| author | Cédric Le Goater <clg@kaod.org> | 2022-08-09 17:38:46 +0200 |
|---|---|---|
| committer | Daniel Henrique Barboza <danielhb413@gmail.com> | 2022-08-31 14:08:06 -0300 |
| commit | 5b0f170a8aa2b83d04aa6769eef35013a24ac52f (patch) | |
| tree | 2c04fccd5fcbdd1a8b4e0a2fa0717cae7be0136d /hw/ppc/ppc405.h | |
| parent | 3b758ca2f05fccd73b49cf88eff7d2dbf489902e (diff) | |
| download | qemu-5b0f170a8aa2b83d04aa6769eef35013a24ac52f.zip qemu-5b0f170a8aa2b83d04aa6769eef35013a24ac52f.tar.gz qemu-5b0f170a8aa2b83d04aa6769eef35013a24ac52f.tar.bz2 | |
ppc/ppc405: Start QOMification of the SoC
This moves all the code previously done in the ppc405ep_init() routine
under ppc405_soc_realize(). We can also adjust the number of banks now
that we have control on ppc4xx_sdram_init().
Signed-off-by: Cédric Le Goater <clg@kaod.org>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-Id: <20220809153904.485018-7-clg@kaod.org>
Signed-off-by: Daniel Henrique Barboza <danielhb413@gmail.com>
Diffstat (limited to 'hw/ppc/ppc405.h')
| -rw-r--r-- | hw/ppc/ppc405.h | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/hw/ppc/ppc405.h b/hw/ppc/ppc405.h index 66dc21c..dc862bc 100644 --- a/hw/ppc/ppc405.h +++ b/hw/ppc/ppc405.h @@ -73,9 +73,14 @@ struct Ppc405SoCState { /* Public */ MemoryRegion ram_banks[2]; hwaddr ram_bases[2], ram_sizes[2]; + bool do_dram_init; MemoryRegion *dram_mr; hwaddr ram_size; + + uint32_t sysclk; + PowerPCCPU *cpu; + DeviceState *uic; }; /* PowerPC 405 core */ @@ -84,11 +89,4 @@ ram_addr_t ppc405_set_bootinfo(CPUPPCState *env, ram_addr_t ram_size); void ppc4xx_plb_init(CPUPPCState *env); void ppc405_ebc_init(CPUPPCState *env); -PowerPCCPU *ppc405ep_init(MemoryRegion *address_space_mem, - MemoryRegion ram_memories[2], - hwaddr ram_bases[2], - hwaddr ram_sizes[2], - uint32_t sysclk, DeviceState **uicdev, - int do_init); - #endif /* PPC405_H */ |