aboutsummaryrefslogtreecommitdiff
path: root/hw/ppc/pnv_lpc.c
diff options
context:
space:
mode:
authorCédric Le Goater <clg@kaod.org>2018-06-15 17:25:34 +0200
committerDavid Gibson <david@gibson.dropbear.id.au>2018-06-21 21:22:53 +1000
commit04026890f2d71afb36dbef24c370171cd0c42913 (patch)
tree858bac5763c165b4e00d47f1f9afa246d7489d67 /hw/ppc/pnv_lpc.c
parentd35aefa9ae150a8a5943ca3d9102020a5382de0b (diff)
downloadqemu-04026890f2d71afb36dbef24c370171cd0c42913.zip
qemu-04026890f2d71afb36dbef24c370171cd0c42913.tar.gz
qemu-04026890f2d71afb36dbef24c370171cd0c42913.tar.bz2
ppc/pnv: introduce a new isa_create() operation to the chip model
This moves the details of the ISA bus creation under the LPC model but more important, the new PnvChip operation will let us choose the chip class to use when we introduce the different chip classes for Power9 and Power8. It hides away the processor chip controllers from the machine. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Diffstat (limited to 'hw/ppc/pnv_lpc.c')
-rw-r--r--hw/ppc/pnv_lpc.c30
1 files changed, 25 insertions, 5 deletions
diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c
index 402c4fe..d772132 100644
--- a/hw/ppc/pnv_lpc.c
+++ b/hw/ppc/pnv_lpc.c
@@ -22,6 +22,7 @@
#include "target/ppc/cpu.h"
#include "qapi/error.h"
#include "qemu/log.h"
+#include "hw/isa/isa.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_lpc.h"
@@ -535,16 +536,35 @@ static void pnv_lpc_isa_irq_handler(void *opaque, int n, int level)
}
}
-qemu_irq *pnv_lpc_isa_irq_create(PnvLpcController *lpc, int chip_type,
- int nirqs)
+ISABus *pnv_lpc_isa_create(PnvLpcController *lpc, bool use_cpld, Error **errp)
{
+ Error *local_err = NULL;
+ ISABus *isa_bus;
+ qemu_irq *irqs;
+ qemu_irq_handler handler;
+
+ /* let isa_bus_new() create its own bridge on SysBus otherwise
+ * devices speficied on the command line won't find the bus and
+ * will fail to create.
+ */
+ isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return NULL;
+ }
+
/* Not all variants have a working serial irq decoder. If not,
* handling of LPC interrupts becomes a platform issue (some
* platforms have a CPLD to do it).
*/
- if (chip_type == PNV_CHIP_POWER8NVL) {
- return qemu_allocate_irqs(pnv_lpc_isa_irq_handler, lpc, nirqs);
+ if (use_cpld) {
+ handler = pnv_lpc_isa_irq_handler_cpld;
} else {
- return qemu_allocate_irqs(pnv_lpc_isa_irq_handler_cpld, lpc, nirqs);
+ handler = pnv_lpc_isa_irq_handler;
}
+
+ irqs = qemu_allocate_irqs(handler, lpc, ISA_NUM_IRQS);
+
+ isa_bus_irqs(isa_bus, irqs);
+ return isa_bus;
}