diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-01-24 21:35:22 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2007-01-24 21:35:22 +0000 |
| commit | e6a71ae327a388723182a504bb253777ec36869b (patch) | |
| tree | 750f4dd1de68111a0b9aff96bda7867147b3a2a7 /hw/piix_pci.c | |
| parent | 5f4da8c0f3736b23744c27bf327d012480293b02 (diff) | |
| download | qemu-e6a71ae327a388723182a504bb253777ec36869b.zip qemu-e6a71ae327a388723182a504bb253777ec36869b.tar.gz qemu-e6a71ae327a388723182a504bb253777ec36869b.tar.bz2 | |
Add support for 82371FB (Step A1) and Improved support for 82371SB
(Function 1), by Carlo Marcelo Arenas Belon.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2353 c046a42c-6fe2-441c-8c8c-71466251a162
Diffstat (limited to 'hw/piix_pci.c')
| -rw-r--r-- | hw/piix_pci.c | 27 |
1 files changed, 25 insertions, 2 deletions
diff --git a/hw/piix_pci.c b/hw/piix_pci.c index b2b7bf0..1b16652 100644 --- a/hw/piix_pci.c +++ b/hw/piix_pci.c @@ -246,7 +246,6 @@ static void piix3_reset(PCIDevice *d) pci_conf[0x80] = 0x00; pci_conf[0x82] = 0x00; pci_conf[0xa0] = 0x08; - pci_conf[0xa0] = 0x08; pci_conf[0xa2] = 0x00; pci_conf[0xa3] = 0x00; pci_conf[0xa4] = 0x00; @@ -284,7 +283,6 @@ static void piix4_reset(PCIDevice *d) pci_conf[0x80] = 0x00; pci_conf[0x82] = 0x00; pci_conf[0xa0] = 0x08; - pci_conf[0xa0] = 0x08; pci_conf[0xa2] = 0x00; pci_conf[0xa3] = 0x00; pci_conf[0xa4] = 0x00; @@ -312,6 +310,31 @@ static int piix_load(QEMUFile* f, void *opaque, int version_id) return pci_device_load(d, f); } +int piix_init(PCIBus *bus, int devfn) +{ + PCIDevice *d; + uint8_t *pci_conf; + + d = pci_register_device(bus, "PIIX", sizeof(PCIDevice), + devfn, NULL, NULL); + register_savevm("PIIX", 0, 2, piix_save, piix_load, d); + + piix3_dev = d; + pci_conf = d->config; + + pci_conf[0x00] = 0x86; // Intel + pci_conf[0x01] = 0x80; + pci_conf[0x02] = 0x2E; // 82371FB PIIX PCI-to-ISA bridge + pci_conf[0x03] = 0x12; + pci_conf[0x08] = 0x02; // Step A1 + pci_conf[0x0a] = 0x01; // class_sub = PCI_ISA + pci_conf[0x0b] = 0x06; // class_base = PCI_bridge + pci_conf[0x0e] = 0x80; // header_type = PCI_multifunction, generic + + piix3_reset(d); + return d->devfn; +} + int piix3_init(PCIBus *bus, int devfn) { PCIDevice *d; |